[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v5 6/6] arm/mpu: Provide a constructor for pr_t type
- To: "Orzel, Michal" <Michal.Orzel@xxxxxxx>
- From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
- Date: Thu, 22 May 2025 12:49:58 +0000
- Accept-language: en-GB, en-US
- Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=amd.com smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WAzyU6d9kX4RtXlRuczQHHpwxjnnsPMeEzp+de58qZA=; b=J7EbxDWHu3fDPuFzufXX9Yy3s2kmL1SzWr/d1mzquqxzxqgaCT60iWGvcKhkH/PH5Awbk7u7ycP5flZfQKg+rc5cePTaaoTPHahDpT4fuWZQ5GVQWocx/YMN9/fKvlrd8ZMfpi7W1qzGmMDuDsWPbD7Y8pWh4PpZp2zLTSkyYPoq5lWOO/XUW3fcxynOayFXO6krB5nDE6fyrAwPgodMhdLSF/rNnOvZqpzpP9g9uhYsoELgK4E4aHAC2LOUdOKRTZ9jzTvlh9xn7jP8FLk5mbZuVGhlZVjrrcbwwCYJgIwWi3CwC5u1Xw5asIrhvctAwWCfvDiQIgU+EzixuJlaqA==
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WAzyU6d9kX4RtXlRuczQHHpwxjnnsPMeEzp+de58qZA=; b=RWumEsMi057NGjCEOtL+1aEomaz6Q1q1ZJJELqZiERDmvE5iZSD0E/AqA9ZJhHHy+Q7cqQp2j2M36vFpIgQMivR5u6EgH3mcmPx7FA0T9cv+F/4ZOGRwGlphe+JF4iYFvWonkINZiLPcmSq3P4nL9LfrUUY9vrvDJTpE1BfqYCqtpsDx9F6CFTmupJ1TsPCF+KPYVjeKPIiPG08hLtCWSX8T/jPd3aBgOLxd+LiTTJBIuMd5yVlXdHjiDllVXFPhZVlAzZxYqgkXUNQZ2Crrxp2SXvYOAtB4GmnKdr0nA7XSEcCEiRWQu0GtglhWdj1MiksLrU8S6pnAK1aF0v0eCA==
- Arc-seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=DGXgiwJdyTNKFPplPIQUXvkXxZdRkxzXj/y2cFgobnacbNj+yAb1T8Ngg5FEjsytfhg10x0EDaiZBlg60ZOF37fhaHM+YAalYAk0erxJ+fL6okWviYdD0ymXab0vYa8pobHLoGAE32Vteojc8W9H3i/E820mCXsXcsJc1iLzEE5X1d98Nw2qb2cGKlsmxEFsdB7Bp/WZEtqIw7MWLBV4BDtpbcc3TjtrxtAdatBcOY3OiiPcch+N8nG2eKZfsLgaZJeAyqahbby6bUWrJp/xv3HBDvO/X72yp2l2lfy5x1w0aJbawBbO+G8vjl7MTiDWpWb5ne7IONqCoxsu3tp1AQ==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dfafZ3Zh35X763bbtIWsqZqrTG2sa9bJd2jP6y0hnQbBb4pX+TLqZtXdmLt1pL4mpu2Xaagi1lQTuwjCA3nDm7RjnJ82LIg1czUgtfYjLS+15z2GCNLWLr7FfkdlM2HXx39V8afOQTJfK9aK5gxUK5piGWvHm3wDlNKmvIYNw7tGbyweVTUYfsCoaya5ZaO9i69y8M87l/WObLNqPGdDqVbgObqYC1g6E8Eh8CEk0oTd29NeeskisVVfk3bDXz9SRmEqEJCvGnRAfRvxRCzOEP0t4dRlTWCNkKXoa9SoGQ0TTuwbwlveViHiEz1AppAfUqxRji0Bx0qjKQDOOVWzHA==
- Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Thu, 22 May 2025 12:50:40 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Thread-index: AQHbw+N/uOYJE2XMKkGQJY+Wc9WWnLPebdYAgAA6SoA=
- Thread-topic: [PATCH v5 6/6] arm/mpu: Provide a constructor for pr_t type
Hi Michal,
>> +
>> +pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags)
>> +{
>> + unsigned int attr_idx = PAGE_AI_MASK(flags);
>> + prbar_t prbar;
>> + prlar_t prlar;
>> + pr_t region;
>> +
>> + /* Build up value for PRBAR_EL2. */
>> + prbar = (prbar_t) {
>> + .reg = {
>> + .ro = PAGE_RO_MASK(flags),
>> + .xn = PAGE_XN_MASK(flags),
> Shouldn't you also initialize .xn_0 and .ap_0 or you rely on compound literal
> implicit zero initialization of unspecified fields? But then you do initialize
> .ns to 0 fror prlar...
Yes, because there I would like to specify that value 0 means Hyp in secure
world,
but of course if you want I can explicitly initialise also these two
>
>> + }};
>> +
>> + switch ( attr_idx )
>> + {
>> + /*
>> + * ARM ARM: Shareable, Inner Shareable, and Outer Shareable Normal
>> memory
>> + * (DDI 0487L.a B2.10.1.1.1 Note section):
>> + *
>> + * Because all data accesses to Non-cacheable locations are data
>> coherent
>> + * to all observers, Non-cacheable locations are always treated as Outer
>> + * Shareable
>> + *
>> + * ARM ARM: Device memory (DDI 0487L.a B2.10.2)
>> + *
>> + * All of these memory types have the following properties:
>> + * [...]
>> + * - Data accesses to memory locations are coherent for all observers
>> in
>> + * the system, and correspondingly are treated as being Outer
>> Shareable
>> + */
>> + case MT_NORMAL_NC:
>> + /* Fall through */
>> + case MT_DEVICE_nGnRnE:
>> + /* Fall through */
>> + case MT_DEVICE_nGnRE:
>> + prbar.reg.sh = LPAE_SH_OUTER;
>> + break;
>> + default:
>> + /* Xen mappings are SMP coherent */
>> + prbar.reg.sh = LPAE_SH_INNER;
>> + break;
>> + }
>> +
>> + /* Build up value for PRLAR_EL2. */
>> + prlar = (prlar_t) {
>> + .reg = {
>> + .ns = 0, /* Hyp mode is in secure world */
>> + .ai = attr_idx,
>> + .en = 1, /* Region enabled */
>> + }};
>> +
>> + /* Build up MPU memory region. */
>> + region = (pr_t) {
>> + .prbar = prbar,
>> + .prlar = prlar,
>> + };
>> +
>> + /* Set base address and limit address. */
>> + pr_set_base(®ion, base);
>> + pr_set_limit(®ion, limit);
>> +
>> + return region;
>> +}
>> #endif
>>
>> void __init setup_mm(void)
>
> Other than that:
> Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
>
> ~Michal
>
Cheers,
Luca
|