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RE: [PATCH] xen/arm: Enhance IPMMU-VMSA driver robustness and debug output
- To: Julien Grall <julien@xxxxxxx>, "Orzel, Michal" <michal.orzel@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Jahan Murudi <jahan.murudi.zg@xxxxxxxxxxx>
- Date: Mon, 7 Jul 2025 11:24:45 +0000
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- Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
- Delivery-date: Mon, 07 Jul 2025 11:25:11 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHb4c6ALl3IHvqkBEOgbLXzyjOhU7QQXHcAgANRIGCAABW5gIAHh3bAgAAflQCACzRUEA==
- Thread-topic: [PATCH] xen/arm: Enhance IPMMU-VMSA driver robustness and debug output
Hi Julien,
> On 30/06/2025 13:44, Julien Grall wrote:
>> On 25/06/2025 16:53, Julien Grall wrote:
>
>> Hi Jahan,
>
>>>>>> + dsb(sy);
>>>>> Any clue why Linux (mainline) does not do that?
> I understand for the PCI passthrough, Xen will be using stage-2, so in theory
> the stage-1 could be used by the guest OS. But ultimately, this is the same
> PCI device behind. So if it is not coherent, it should be for both stages. Do
> you have any pointer to the documentation that would state otherwise?
You're right - coherency characteristics are identical for both stages. My
earlier understanding was incorrect.
> Note, I just noticed that IOMMU_FEAT_COHERENT_WALK is not set for the IPMMU.
> So the "dsb sy" is coherent. However, I find doubful an IOMMU would have a
> difference of coherency between two stages. So maybe we should set the flag
> either unconditionally or based on a register.
Excellent observation. Current R-car IPMMU doesn't supports coherent walks - we
should indeed set this flag unconditionally.
>> and we must also prevent(minimise) any DMA operations during TLB
>> invalidation( observed some IPMMU hardware limitations in the
documentation) .
> I don't understand what you wrote in parentheses. But isn't it what you wrote
> all true for stage-1?
Correct – the hardware reference doc guidelines about minimizing DMA during
flushes applies globally. This is true for both stage-1 and stage-2.
Given that the patch has already been Acked by Michal, can we proceed with
applying it?
Regards,
Jahan Murudi
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