[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH 6/9] x86/mwait-idle: add Sierra Forest SoC support
Add Sierra Forest SoC C-states, which are C1, C1E, C6S, and C6SP. Sierra Forest SoC is built with modules, each module includes 4 cores (Crestmont microarchitecture). There is one L2 cache per module, shared between the 4 cores. There is no core C6 state, but there is C6S state, which has module scope: when all 4 cores request C6S, the entire module (4 cores + L2 cache) enters the low power state. C6SP state has package scope - when all modules in the package enter C6S, the package enters the power state mode. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@xxxxxxxxxxxxxxx> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 92813fd5b156 Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -950,6 +950,34 @@ static const struct cpuidle_state grr_cs {} }; +static const struct cpuidle_state srf_cstates[] = { + { + .name = "C1", + .flags = MWAIT2flg(0x00), + .exit_latency = 1, + .target_residency = 1, + }, + { + .name = "C1E", + .flags = MWAIT2flg(0x01), + .exit_latency = 2, + .target_residency = 10, + }, + { + .name = "C6S", + .flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 270, + .target_residency = 700, + }, + { + .name = "C6SP", + .flags = MWAIT2flg(0x23) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 310, + .target_residency = 900, + }, + {} +}; + static void cf_check mwait_idle(void) { unsigned int cpu = smp_processor_id(); @@ -1199,6 +1227,11 @@ static const struct idle_cpu idle_cpu_gr .c1e_promotion = C1E_PROMOTION_DISABLE, }; +static const struct idle_cpu idle_cpu_srf = { + .state_table = srf_cstates, + .c1e_promotion = C1E_PROMOTION_DISABLE, +}; + #define ICPU(model, cpu) \ { X86_VENDOR_INTEL, 6, INTEL_FAM6_ ## model, X86_FEATURE_ALWAYS, \ &idle_cpu_ ## cpu} @@ -1248,6 +1281,7 @@ static const struct x86_cpu_id intel_idl ICPU(ATOM_GOLDMONT_D, dnv), ICPU(ATOM_TREMONT_D, snr), ICPU(ATOM_CRESTMONT, grr), + ICPU(ATOM_CRESTMONT_X, srf), {} };
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