Re: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling to support eSPIs

[Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx>]

Hi Volodymyr,

On 22.08.25 15:26, Volodymyr Babchuk wrote:
> 
> Hi Leonid,
> 
> Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx> writes:
> 
>> Hi Volodymyr,
>>
>> On 21.08.25 19:46, Volodymyr Babchuk wrote:
>>>
>>>
>>>
>>> Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx> writes:
>>>
>>>> The Dom0 configuration logic in create_dom0() has been updated
>>>> to account for extended SPIs when supported by the hardware and
>>>> enabled with CONFIG_GICV3_ESPI. These changes ensure the proper
>>>> calculation of the maximum number of SPIs and eSPIs available for Dom0.
>>>>
>>>> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
>>>> enabled, the maximum number of eSPI interrupts is calculated using
>>>> the ESPI_BASE_INTID offset (4096) and limited at 1024, with 32 IRQs
>>>> subtracted. To ensure compatibility with non-Dom0 domains, this
>>>> adjustment is applied by the toolstack during domain creation, while
>>>> for Dom0 it is handled directly during VGIC initialization. If eSPIs
>>>> are not supported, the calculation defaults to using the standard SPI
>>>> range, with a maximum value of 992 interrupt lines as it works now.
>>>>
>>>> Signed-off-by: Leonid Komarianskyi <leonid_komarianskyi@xxxxxxxx>
>>>>
>>>> ---
>>>> Changes in V2:
>>>> - no changes
>>>> ---
>>>>    xen/arch/arm/domain_build.c     | 10 ++++++++++
>>>>    xen/arch/arm/include/asm/vgic.h | 11 +++++++++++
>>>>    2 files changed, 21 insertions(+)
>>>>
>>>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
>>>> index d91a71acfd..fa5abf2dfb 100644
>>>> --- a/xen/arch/arm/domain_build.c
>>>> +++ b/xen/arch/arm/domain_build.c
>>>> @@ -2055,6 +2055,16 @@ void __init create_dom0(void)
>>>>        /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>>>>        dom0_cfg.arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
>>>>        dom0_cfg.arch.nr_spis = VGIC_DEF_NR_SPIS;
>>>> +#ifdef CONFIG_GICV3_ESPI
>>>> +    /*
>>>> +     * Check if the hardware supports extended SPIs (even if the 
>>>> appropriate config is set).
>>>> +     * If not, the common SPI range will be used. Otherwise overwrite the 
>>>> nr_spis with the
>>>> +     * maximum available INTID from eSPI range. In that case, the number 
>>>> of regular SPIs will
>>>> +     * be adjusted to the maximum value during vGIC initialization.
>>>> +     */
>>>> +    if ( gic_number_espis() > 0 )
>>>> +        dom0_cfg.arch.nr_spis = VGIC_DEF_NR_ESPIS;
>>>> +#endif
>>>>        dom0_cfg.arch.tee_type = tee_get_type();
>>>>        dom0_cfg.max_vcpus = dom0_max_vcpus();
>>>>    
>>>> diff --git a/xen/arch/arm/include/asm/vgic.h 
>>>> b/xen/arch/arm/include/asm/vgic.h
>>>> index 9fa4523018..117b3aa92c 100644
>>>> --- a/xen/arch/arm/include/asm/vgic.h
>>>> +++ b/xen/arch/arm/include/asm/vgic.h
>>>> @@ -353,6 +353,17 @@ extern void vgic_check_inflight_irqs_pending(struct 
>>>> vcpu *v,
>>>>    /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. 
>>>> */
>>>>    #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
>>>>    
>>>> +#ifdef CONFIG_GICV3_ESPI
>>>> +/*
>>>> + * Returns the maximum eSPI INTID subtracted by 32. For non-Dom0 domains, 
>>>> the
>>>> + * toolstack applies the same adjustment to cover local IRQs. We will add 
>>>> back
>>>> + * this value during VGIC initialization. This ensures consistent 
>>>> handling for Dom0
>>>> + * and other domains. For the regular SPI range interrupts in this case, 
>>>> the maximum
>>>> + * value of VGIC_DEF_NR_SPIS will be used.
>>>> + */
>>>> +#define VGIC_DEF_NR_ESPIS (ESPI_BASE_INTID + min(gic_number_espis(), 
>>>> 1024U) - 32)
>>> Name of the define is wrong, as it is not number of eSPIs. Actually, this is
>>> maximum SPI (including eSPIs) number.
>>
>>
>> Thank you for your review.
>> Would it be okay if I rename this macro to VGIC_DEF_MAX_SPI?
> 
> Yes, I think this is better name.
> 

Thank you for your confirmation. I will rename this macro to 
VGIC_DEF_MAX_SPI in V3.

Best regards,
Leonid