[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v4 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers
- To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx>
- Date: Thu, 28 Aug 2025 11:41:57 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=epam.com; dmarc=pass action=none header.from=epam.com; dkim=pass header.d=epam.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QTzp5VISobobGwGhn9exeFnV0sYw1kkyUMhxzo6dQOM=; b=y84kK9oQvuq73DK6mNJwfBIhtvCkRUUml2L2bvBZNgwvBAmGgM7iQKN2W8oamA3ohZ5sTGaWUa+zghqZyDmN6C79/rUGff+Exqvj9Y6gWKpZ1Nl+YeCBrhxrGFCe9QtyjLhc+XMhw+2erorf1Jvu/70Ad0eswz7D7Fkvi2L0+NOwIBa8T0Ixdwaji8y+QxLXaNtzg+bB/gSmEze4GSQgdR3hV7avkPaw/QMl/u+pKEEyen4wzIejPOcYxdiV9jHvgUoq5wwxJi2xn3rtrDigjyQhu1SmdfRuU0ZqGab8NFUyCcm26odctbUv140XsKv3ItexGVpqYXoVt4UB9yGz4w==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gFbUp/t636ZVfnqlOxU8KE1pKsmbyhmuwD8LKbO3rKgY5lGp/nLP8BQ1KKjfXNydCcFfhRPo0f7f7n2a0yjMkWEcRSS9+q7PH+6vD42lnt9cz3+/ZcmhFJtsORA88Zru95lvJli5DRS+mKpv0DOJ7cW676J3rdzbhmDKlLnVNd2+92jsrZ0E3WZPcJ+Wk3W78wiPkl4x2XPZ1c35Dw4EcIrlAk3WrvHFTjzQcRvXsUltPGna3ccUB6v2SVkx5k6YyEE7a8bb9MJwEdUb3Ok1V+ypBO8bS4EeS0J5j3jxwfSxPg2/3cSzNpyJAH/kch4xGrkHX+zeLiCDA8uj19gWkA==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com;
- Cc: "olekstysh@xxxxxxxxx" <olekstysh@xxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Thu, 28 Aug 2025 11:42:09 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHcF3/PMGQJ9ZKjmEOWPrVRdE59HbR38oSA
- Thread-topic: [PATCH v4 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers
Hello everyone,
Sorry for spamming, but according to the comments on the 8th patch of
the series:
https://patchew.org/Xen/cover.1756317702.git.leonid._5Fkomarianskyi@xxxxxxxx/9e8a11b024833c1b91b8806e7708bf35b04a8f6e.1756317702.git.leonid._5Fkomarianskyi@xxxxxxxx/
As has_espi field will be removed, the following:
On 27.08.25 21:24, Leonid Komarianskyi wrote:
> @@ -1184,6 +1396,21 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,
> mmio_info_t *info,
> case VRANGE32(0x005C, 0x007C):
> goto read_reserved;
>
> +#ifdef CONFIG_GICV3_ESPI
> + case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> + case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> + case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> + case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> + case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> + case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> + case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> + case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> + case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> + case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
> + if ( !v->domain->arch.vgic.has_espi )
...and similar code will be changed to the macro:
#define has_espi(v) ((v)->domain->arch.vgic.nr_espis != 0)
It will behave in a similar way, without any functional changes,
assuming this solution is acceptable.
Best regards,
Leonid
|
