Re: [PATCH v1 3/9] parisc: Convert DMA map_page to map_phys interface

[James Bottomley <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx>]

On Fri, 2025-10-03 at 12:01 -0300, Jason Gunthorpe wrote:
> On Sun, Sep 28, 2025 at 06:02:23PM +0300, Leon Romanovsky wrote:
> > +ccio_map_phys(struct device *dev, phys_addr_t phys, size_t size,
> > +         enum dma_data_direction direction, unsigned long
> > attrs)
> >  {
> > -   return ccio_map_single(dev, page_address(page) + offset,
> > size,
> > -                   direction);
> > +   if (attrs & DMA_ATTR_MMIO)
> > +           return DMA_MAPPING_ERROR;
> > +
> > +   return ccio_map_single(dev, phys_to_virt(phys), size,
> > direction);
> 
> This doesn't actually use the virt at all:
> 
>       offset = ((unsigned long) addr) & ~IOVP_MASK;
>       if((size % L1_CACHE_BYTES) || ((unsigned long)addr %
> L1_CACHE_BYTES))
>               ccio_io_pdir_entry(pdir_start, KERNEL_SPACE,
> (unsigned long)addr, hint);

Actually, it does: it has to; parisc caches are VIPT.  The iommu needs
to know both the physical address and the virtual tag (also called the
coherence index) to instruct the CPU to flush its cache.  The sole use
of the vba is in ccio_io_pdir_entry() which programs the IOMMU page
table.  The coherence index is pretty small because the largest VIPT
cache stride parisc has is 4MB and obviously the lower 12 bits (page
offset) are the same for both physical and virtual, so it's only the 10
bits between 4k and 4M that the iommu needs (the entry is 12 bits
because architecturally there were chips with a 16M stride planned for
but never produced).

> 
> And ccio_io_pdir_entry():
>       pa = lpa(vba);
> 
> Is a special instruction that uses virt but AI tells me that special
> LPA instruction is returning phys. Not sure if that is a different
> value than virt_to_phys()..

That's right, so if you want to pass both phys and virt addresses to
the function, this could be dropped.

Regards,

James