[PATCH 2/4] x86: Split out Intel-specific code to be executed without ucode loading

[Alejandro Vallejo <alejandro.garciavallejo@xxxxxxx>]

Some code must be executed even with microcode loading disabled to find
out the current microcode revision. This is important to determine active
erratas and such.

With the intent of stripping microcode loading via Kconfig, move such
essential Intel-specific code to an intel-base.c file.

Not a functional change.

Signed-off-by: Alejandro Vallejo <alejandro.garciavallejo@xxxxxxx>
---
 xen/arch/x86/cpu/microcode/Makefile     |  1 +
 xen/arch/x86/cpu/microcode/intel-base.c | 48 +++++++++++++++++++++
 xen/arch/x86/cpu/microcode/intel.c      | 56 ++++---------------------
 xen/arch/x86/cpu/microcode/intel.h      | 16 +++++++
 4 files changed, 72 insertions(+), 49 deletions(-)
 create mode 100644 xen/arch/x86/cpu/microcode/intel-base.c
 create mode 100644 xen/arch/x86/cpu/microcode/intel.h

diff --git a/xen/arch/x86/cpu/microcode/Makefile 
b/xen/arch/x86/cpu/microcode/Makefile
index 00aa0f24e4..74289981e3 100644
--- a/xen/arch/x86/cpu/microcode/Makefile
+++ b/xen/arch/x86/cpu/microcode/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_AMD) += amd.o
 obj-$(CONFIG_AMD) += amd-base.o
 obj-y += core.o
 obj-$(CONFIG_INTEL) += intel.o
+obj-$(CONFIG_INTEL) += intel-base.o
diff --git a/xen/arch/x86/cpu/microcode/intel-base.c 
b/xen/arch/x86/cpu/microcode/intel-base.c
new file mode 100644
index 0000000000..4fcacaa192
--- /dev/null
+++ b/xen/arch/x86/cpu/microcode/intel-base.c
@@ -0,0 +1,48 @@
+#include <xen/init.h>
+
+#include <asm/msr.h>
+#include <asm/processor.h>
+
+#include "intel.h"
+
+#define pr_debug(x...) ((void)0)
+
+static void cf_check collect_cpu_info(void)
+{
+    struct cpu_signature *csig = &this_cpu(cpu_sig);
+    uint64_t msr_content;
+
+    memset(csig, 0, sizeof(*csig));
+
+    rdmsrl(MSR_IA32_PLATFORM_ID, msr_content);
+    csig->pf = 1 << ((msr_content >> 50) & 7);
+
+    /*
+     * Obtaining the microcode version involves writing 0 to the "read only"
+     * UCODE_REV MSR, executing any CPUID instruction, after which a nonzero
+     * revision should appear.
+     */
+    wrmsrl(MSR_IA32_UCODE_REV, 0);
+    csig->sig = cpuid_eax(1);
+    rdmsrl(MSR_IA32_UCODE_REV, msr_content);
+    csig->rev = msr_content >> 32;
+
+    pr_debug("microcode: collect_cpu_info : sig=%#x, pf=%#x, rev=%#x\n",
+             csig->sig, csig->pf, csig->rev);
+}
+
+static const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = {
+    .cpu_request_microcode = intel_cpu_request_microcode,
+    .apply_microcode       = intel_apply_microcode,
+    .collect_cpu_info      = collect_cpu_info,
+    .compare               = intel_compare,
+    .cpio_path             = intel_cpio_path,
+};
+
+void __init ucode_probe_intel(struct microcode_ops *ops)
+{
+    *ops = intel_ucode_ops;
+
+    if ( !intel_can_load_microcode() )
+        ops->apply_microcode = NULL;
+}
diff --git a/xen/arch/x86/cpu/microcode/intel.c 
b/xen/arch/x86/cpu/microcode/intel.c
index 281993e725..c5e0012a03 100644
--- a/xen/arch/x86/cpu/microcode/intel.c
+++ b/xen/arch/x86/cpu/microcode/intel.c
@@ -31,9 +31,7 @@
 #include <asm/processor.h>
 #include <asm/system.h>
 
-#include "private.h"
-
-#define pr_debug(x...) ((void)0)
+#include "intel.h"
 
 struct microcode_patch {
     uint32_t hdrver;
@@ -120,30 +118,6 @@ static bool signature_matches(const struct cpu_signature 
*cpu_sig,
     return cpu_sig->pf & ucode_pf;
 }
 
-static void cf_check collect_cpu_info(void)
-{
-    struct cpu_signature *csig = &this_cpu(cpu_sig);
-    uint64_t msr_content;
-
-    memset(csig, 0, sizeof(*csig));
-
-    rdmsrl(MSR_IA32_PLATFORM_ID, msr_content);
-    csig->pf = 1 << ((msr_content >> 50) & 7);
-
-    /*
-     * Obtaining the microcode version involves writing 0 to the "read only"
-     * UCODE_REV MSR, executing any CPUID instruction, after which a nonzero
-     * revision should appear.
-     */
-    wrmsrl(MSR_IA32_UCODE_REV, 0);
-    csig->sig = cpuid_eax(1);
-    rdmsrl(MSR_IA32_UCODE_REV, msr_content);
-    csig->rev = msr_content >> 32;
-
-    pr_debug("microcode: collect_cpu_info : sig=%#x, pf=%#x, rev=%#x\n",
-             csig->sig, csig->pf, csig->rev);
-}
-
 /*
  * Sanity check a blob which is expected to be a microcode patch.  The 48 byte
  * header is of a known format, and together with totalsize are within the
@@ -273,7 +247,7 @@ static bool microcode_fits_cpu(const struct microcode_patch 
*mc)
     return false;
 }
 
-static int cf_check intel_compare(
+int cf_check intel_compare(
     const struct microcode_patch *old, const struct microcode_patch *new)
 {
     /*
@@ -286,8 +260,8 @@ static int cf_check intel_compare(
     return compare_revisions(old->rev, new->rev);
 }
 
-static int cf_check apply_microcode(const struct microcode_patch *patch,
-                                    unsigned int flags)
+int cf_check intel_apply_microcode(const struct microcode_patch *patch,
+                                   unsigned int flags)
 {
     uint64_t msr_content;
     unsigned int cpu = smp_processor_id();
@@ -333,7 +307,7 @@ static int cf_check apply_microcode(const struct 
microcode_patch *patch,
     return 0;
 }
 
-static struct microcode_patch *cf_check cpu_request_microcode(
+struct microcode_patch *cf_check intel_cpu_request_microcode(
     const void *buf, size_t size, bool make_copy)
 {
     int error = 0;
@@ -391,7 +365,7 @@ static struct microcode_patch *cf_check 
cpu_request_microcode(
     return patch;
 }
 
-static bool __init can_load_microcode(void)
+bool __init intel_can_load_microcode(void)
 {
     uint64_t mcu_ctrl;
 
@@ -404,21 +378,5 @@ static bool __init can_load_microcode(void)
     return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD);
 }
 
-static const char __initconst intel_cpio_path[] =
+const char __initconst intel_cpio_path[] =
     "kernel/x86/microcode/GenuineIntel.bin";
-
-static const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = {
-    .cpu_request_microcode            = cpu_request_microcode,
-    .collect_cpu_info                 = collect_cpu_info,
-    .apply_microcode                  = apply_microcode,
-    .compare                          = intel_compare,
-    .cpio_path                        = intel_cpio_path,
-};
-
-void __init ucode_probe_intel(struct microcode_ops *ops)
-{
-    *ops = intel_ucode_ops;
-
-    if ( !can_load_microcode() )
-        ops->apply_microcode = NULL;
-}
diff --git a/xen/arch/x86/cpu/microcode/intel.h 
b/xen/arch/x86/cpu/microcode/intel.h
new file mode 100644
index 0000000000..3c1419dc77
--- /dev/null
+++ b/xen/arch/x86/cpu/microcode/intel.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef ASM_X86_MICROCODE_INTEL_H
+#define ASM_X86_MICROCODE_INTEL_H
+
+#include "private.h"
+
+bool intel_can_load_microcode(void);
+int cf_check intel_compare(const struct microcode_patch *old,
+                           const struct microcode_patch *new);
+int cf_check intel_apply_microcode(const struct microcode_patch *patch,
+                                   unsigned int flags);
+struct microcode_patch *cf_check intel_cpu_request_microcode(
+    const void *buf, size_t size, bool make_copy);
+extern const char intel_cpio_path[];
+
+#endif /* ASM_X86_MICROCODE_INTEL_H */
-- 
2.43.0