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Re: [PATCH] xen/arm: gic-v3: disable Group 1 before CPU power-down
- To: Mykola Kvach <xakep.amatop@xxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: "Orzel, Michal" <michal.orzel@xxxxxxx>
- Date: Fri, 10 Apr 2026 10:17:55 +0200
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- Cc: Mykola Kvach <mykola_kvach@xxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Fri, 10 Apr 2026 08:18:08 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 10/04/2026 09:47, Mykola Kvach wrote:
> From: Mykola Kvach <mykola_kvach@xxxxxxxx>
>
> gicv3_cpu_disable() currently writes 0 to ICC_CTLR_EL1. Unlike
> GICC_CTLR in the GICv2 path, ICC_CTLR_EL1 does not enable or disable
> physical Group 1 interrupt signalling, so this write only clears
> EOImode.
>
> The GICv3 power management rules require the physical group enables in
> the CPU interface to be cleared before the redistributor is driven into
> ProcessorSleep, otherwise behaviour is UNPREDICTABLE. Xen only enables
> Group 1 interrupts on this path, so disable the interface by clearing
> ICC_IGRPEN1_EL1 instead.
>
> This appears to be a copy of the GICv2 pattern where the enable control
> lives in CTLR, but for GICv3 the enable moved to ICC_IGRPEN1_EL1.
Yes, GICv2 GICC_CTLR combines enable+EOImode in one register.
>
> Fixes: bc183a0235e ("xen/arm: Add support for GIC v3")
> Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
~Michal
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