Re: [PATCH v3 02/23] xen/arm: smmuv3: Add support for stage-1 and nested stage translation

[Milan Djokic <milan_djokic@xxxxxxxx>]

Hi Luca,

On 4/10/26 11:49, Luca Fancellu wrote:
> Hi Milan,
>
> > @@ -740,7 +766,33 @@ static void arm_smmu_write_strtab_ent(struct 
> > arm_smmu_master *master, u32 sid,
> > return;
> > }
> >
> > + if (ste_live) {
> > + /* First invalidate the live STE */
> > + dst[0] = cpu_to_le64(STRTAB_STE_0_CFG_ABORT);
> > + arm_smmu_sync_ste_for_sid(smmu, sid);
> > + }
> > +
> > + if (s1_cfg) {
> > + BUG_ON(s1_live);
> I think this is wrong, if a guest issues another s1 update on the same sid, 
> this will crash Xen, I think
> that we’ve already invalidated the live status so this one should be removed
Yes, this is a leftover. I will remove this assertion.

> > + dst[1] = cpu_to_le64(
> > + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) |
> > + FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
> > + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
> > + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |
> > + FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1));
> > +
> > + if (smmu->features & ARM_SMMU_FEAT_STALLS &&
> > +   !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
> > + dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
> > +
> > + val |= (s1_cfg->s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK) |
> > + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) |
> > + FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) |
> > + FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt);
> > + }
> > +
> > if (s2_cfg) {
> > + u64 vttbr = s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK;
> > u64 strtab =
> > FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) |
> > FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) |
> > @@ -750,12 +802,19 @@ static void arm_smmu_write_strtab_ent(struct 
> > arm_smmu_master *master, u32 sid,
> > STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
> > STRTAB_STE_2_S2R;
> >
> > - BUG_ON(ste_live);
> > + if (s2_live) {
> > + u64 s2ttb = le64_to_cpu(dst[3]) & STRTAB_STE_3_S2TTB_MASK;
> > + BUG_ON(s2ttb != vttbr);
> > + }
> > +
> > dst[2] = cpu_to_le64(strtab);
> >
> > - dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
> > + dst[3] = cpu_to_le64(vttbr);
> >
> > val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
> > + } else {
> > + dst[2] = 0;
> > + dst[3] = 0;
> > }
> >
> > if (master->ats_enabled)
> > @@ -1254,6 +1313,15 @@ static int arm_smmu_domain_finalise(struct iommu_domain 
> > *domain,
> > {
> > int ret;
> > struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
> > + struct arm_smmu_device *smmu = smmu_domain->smmu;
> > +
> > + if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED &&
> > + (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) ||
> > + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2))) {
> > + dev_info(smmu_domain->smmu->dev,
> > + "does not implement two stages\n");
> > + return -EINVAL;
> > + }
> >
> > /* Restrict the stage to what we can actually support */
> > smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
> Here we set stage 2 as default, but in arm_smmu_device_hw_probe() we’ve
> deleted the check for S2 required, so if we have an HW with only S1 the probe 
> will
> succeed but we will wrongly set here S2, so I would keep ...
Yes, handling of stage-1-only scenario is not correct, missing in ste 
and guest config handling also. I will update this in the new version.
Following comments from Julien on the same topic, I'm wondering if it's 
valid to provide stage-1-only support in Xen?
> > @@ -2353,11 +2421,14 @@ static int arm_smmu_device_hw_probe(struct 
> > arm_smmu_device *smmu)
> > break;
> > }
> >
> > + if (reg & IDR0_S1P)
> > + smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
> > +
> > if (reg & IDR0_S2P)
> > smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
> >
> > - if (!(reg & IDR0_S2P)) {
> > - dev_err(smmu->dev, "no stage-2 translation support!\n");
> this change, rearranged in the way that is sensible with the new logic.
>
> > + if (!(reg & (IDR0_S1P | IDR0_S2P))) {
> > + dev_err(smmu->dev, "no translation support!\n");
> > return -ENXIO;
> > }
Best regards,
Milan