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Re: [PATCH] xen/arm: gic-v3: Preserve ARE_NS when disabling the distributor
- To: Mykola Kvach <xakep.amatop@xxxxxxxxx>
- From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
- Date: Tue, 19 May 2026 20:31:08 +0000
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Mykola Kvach <mykola_kvach@xxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
- Delivery-date: Tue, 19 May 2026 20:32:40 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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- Thread-topic: [PATCH] xen/arm: gic-v3: Preserve ARE_NS when disabling the distributor
Hi Mykola,
> On 19 May 2026, at 15:31, Mykola Kvach <xakep.amatop@xxxxxxxxx> wrote:
>
> From: Mykola Kvach <mykola_kvach@xxxxxxxx>
>
> gicv3_dist_init() disables the distributor before reprogramming the
> global interrupt state. It used to do this by writing 0 to GICD_CTLR.
>
> On a system where firmware has already enabled Non-secure affinity
> routing, a zero write clears the Non-secure view's GICD_CTLR.ARE_NS bit.
> Arm IHI 0069H.b, section 2.3.3 ("Changing affinity routing enables"),
> states that changing GICD_CTLR.ARE_NS from 1 to 0 is UNPREDICTABLE. The
> GICD_CTLR register description in section 12.9.4 carries the same rule
> for the ARE_NS field.
>
> Preserve ARE_NS while clearing the group enable bits. If firmware left
> ARE_NS clear, the value written is still 0, preserving the existing
> initialization flow.
>
> Fixes: bc183a0235e0 ("xen/arm: Add support for GIC v3")
> Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
> ---
Looks ok to me and aligned to the specifications, bit 4 is preserved on both
Armv8-A (ARE_NS) and Armv8-R (ARE).
Reviewed-by: Luca Fancellu <luca.fancellu@xxxxxxx>
Cheers,
Luca
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