[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v1 1/6] nestedsvm: Fix CR3 MBZ check
- To: xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Ross Lagerwall <ross.lagerwall@xxxxxxxxxx>
- Date: Tue, 26 May 2026 13:40:22 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sv/Y4EwXju23E48lt//vpB4H/fw+tt8XO+BDmxPLuYM=; b=h8Izpc5aQItdrjFV8Dmm2b1ZzFmmIuPbglTZbPDlEVtsIU4Yaq6ipMEj5AbLfqz8D1idLdFOckKxZJ0ETzyX7zqkaW8UyfUrTo6FO+9K8OSu+oPLXj2j6WOVk1uM2lIJQcCwt1STkHg02/k7M/b53MFmN8cYq0aQ4545knD6hYbDgWjrGbMIH0w/bk7HGJO2+R3O7ri/ywzZi+Bl0r4/uUN5QZxZXPBLx0kg+t9Ihvurpprfk+62yU1XehkNAVxjkOf8UMlgo65mJofhAwUC1rJACYDEemjt9Nin7xZmASPuH9ROK6HK2my1vPXnV35x12V4FdEKwEsK7uMWiJiLwQ==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PklUqcutca3orV9sKL2JtB7bZBfySLrrMYfH5NCky0rOBExpX9LjPLnbOJ+E54FLBXYllwnDFiq/EAdiQsZ5/EO0D94Xw5E1PunYoibYB4I/ZyrN6Z0Idl6O50OKqnpIEUWkNTkiIDr26P3mrOB4V3uon4kASx6FKudn1KTXjWjA6+E7nBtArUiCfoiC1SNNDnK5mRduUgVnsdVGft2NAxZdcdNYomrribGnBJeWEali4/lsz3A1Ni+kBQ0Rg+LOKe/E6/m6BZVO4uMaNVjc9rWIGvw+FmtYyeXUJb7BX+UV9hWofohLlK+5sZCpBsirkru0ARn0B9P4dz2wfZovhQ==
- Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=citrix.com header.i="@citrix.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: Ross Lagerwall <ross.lagerwall@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Jason Andryuk <jason.andryuk@xxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>
- Delivery-date: Tue, 26 May 2026 12:41:06 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
The existing code checks for any reserved bit set while the APM only
considers it invalid if an MBZ bit is set. Relax the check to match the
APM and hardware.
Some of the reserved bits were observed to be set running Rocky Linux
10.1 on Xen on Xen.
Fixes: 9a779e4fc161 ("Implement SVM specific part for Nested Virtualization")
Signed-off-by: Ross Lagerwall <ross.lagerwall@xxxxxxxxxx>
---
xen/arch/x86/hvm/svm/vmcb.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
index 975a1eaef806..9ada491e57db 100644
--- a/xen/arch/x86/hvm/svm/vmcb.c
+++ b/xen/arch/x86/hvm/svm/vmcb.c
@@ -347,10 +347,8 @@ bool svm_vmcb_isvalid(
PRINTF("CR0: bits [63:32] are not zero (%#"PRIx64")\n", cr0);
if ( (cr0 & X86_CR0_PG) &&
- ((cr3 & 7) ||
- ((!(cr4 & X86_CR4_PAE) || (efer & EFER_LMA)) && (cr3 & 0xfe0)) ||
- ((efer & EFER_LMA) &&
- (cr3 >> v->domain->arch.cpuid->extd.maxphysaddr))) )
+ ((efer & EFER_LMA) &&
+ (cr3 >> v->domain->arch.cpuid->extd.maxphysaddr)) )
PRINTF("CR3: MBZ bits are set (%#"PRIx64")\n", cr3);
valid = hvm_cr4_guest_valid_bits(v->domain);
--
2.53.0
|
