[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v1 00/17] [RISC-V] virtual interrupt controller (vAPLIC/vIMSIC) support


  • To: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Mon, 27 Jul 2026 17:21:55 +0200
  • Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=suse.com header.i="@suse.com" header.h="Content-Transfer-Encoding:Content-Type:In-Reply-To:Autocrypt:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID"
  • Autocrypt: addr=jbeulich@xxxxxxxx; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL
  • Cc: Romain Caritey <Romain.Caritey@xxxxxxxxxxxxx>, Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>, Alistair Francis <alistair.francis@xxxxxxx>, Connor Davis <connojdavis@xxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Julien Grall <julien@xxxxxxx>, Roger Pau Monné <roger@xxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Mon, 27 Jul 2026 15:22:01 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 20.07.2026 18:01, Oleksii Kurochko wrote:
> Hi all,
> 
> This series adds the initial virtual interrupt controller (vINTC) support
> for RISC-V guests in Xen, based on the Advanced Interrupt Architecture
> (AIA): a virtual APLIC (vAPLIC) in MSI mode backed by a virtual IMSIC
> (vIMSIC) using hardware guest interrupt files.
> 
> Rather than emulating APLIC in direct-delivery mode (which requires
> trap-and-emulate for every interrupt and is costly), the series targets
> IMSIC from the start. AIA lets a hart implement several "guest interrupt
> files" (up to GEILEN), so external interrupts can be delivered to a vCPU
> directly by hardware via the VGEIN field of hstatus, without a hypervisor
> round-trip. Xen only has to emulate the APLIC MMIO programming interface
> and route the guest's intent onto the physical MSI topology; interrupt
> delivery itself stays in hardware.
> 
> The work breaks down into a few logical blocks:
> 
> Physical APLIC/AIA groundwork (patches 1-3)
>   - Correctly track IRQ_DISABLED across runtime enable/disable and order
>     the ->status update against the IMSIC CSR write.
>   - Per-pCPU VGEIN (guest interrupt file) allocator: assign/release a
>     hardware guest file to a vCPU and program hstatus.VGEIN.
>   - Add the missing APLIC register offsets/masks needed by both the
>     physical and virtual APLIC code (no functional change).
> 
> Device-agnostic MMIO dispatch + vAPLIC emulation (patches 4-5)
>   - A per-domain MMIO handler table modelled on Arm's framework, so
>     emulated devices self-register their GPA ranges and the fault path
>     stays agnostic via a single try_handle_mmio() entry point.
>   - vAPLIC MMIO read/write emulation. Writes are gated by the domain's
>     authorised-IRQ bitmap so a guest cannot touch interrupts it does not
>     own, and TARGET writes are translated from virtual to physical
>     hart/guest-file indices. Delegation (SOURCECFG.D) is not yet
>     supported.
> 
> vIMSIC guest interrupt files and state (patches 6-9)
>   - Stage-2 map a vCPU's physical guest interrupt file to the fixed
>     per-vCPU GPA page the guest expects at offset 0.
>   - vcpu_aia_init(): assign a VGEIN, map its guest file and record the
>     IMSIC state as a consistent unit.
>   - IMSIC state save/restore (currently tracking which pCPU owns the
>     guest file, needed because the pCPU id is part of the MSI address).
>   - has_msi_support() helper to decide whether IMSIC state has to be
>     saved/restored.
> 
> vINTC state save/restore plumbing (patches 10-11)
>   - vintc_state_{save,restore}() wrappers over new store/restore hooks in
>     struct vintc_ops, and the vAPLIC implementation of those hooks. No
>     callers are wired up yet; the context-switch calls arrive with vCPU
>     context switch support.
> 
> Trap and instruction emulation infrastructure (patches 12-17)
>   - Extend the exception-table format with type/data fields and add
>     EX_TYPE_TRAP_INFO so fixups can capture sepc/scause/stval.
>   - riscv_vcpu_unpriv_read() (HLV/HLVX) to read guest memory/instructions
>     safely, and riscv_vcpu_trap_redirect() to forward a synchronous trap
>     back into the guest's VS-mode handler.
>   - A guest page-fault handler that decodes the trapped load/store
>     instruction (HTINST, or an unprivileged fetch as a fallback) and
>     dispatches the MMIO access through try_handle_mmio().
> 
> Note on versioning: the series is posted as v1 as a freshly split-out
> series, but several patches carry v2/v3 changelogs because they were
> previously circulated as part of a larger another patches [1] from which the
> current depends.
> 
> CI tests: 
> https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2690874319
> 
> [1] 
> https://lore.kernel.org/xen-devel/cover.1784559209.git.oleksii.kurochko@xxxxxxxxx/T/#t
> 
> Oleksii Kurochko (17):
>   xen/riscv: manage IRQ_DISABLED flag in APLIC irq enable/disable
>     callbacks
>   xen/riscv: add basic VGEIN management for AIA guests
>   xen/riscv: add missing APLIC register offsets, masks to asm/aplic.h
>   xen/riscv: introduce device-agnostic MMIO emulation dispatch
>   xen/riscv: implement virtual APLIC MMIO emulation
>   xen/riscv: map IMSIC interrupt file for vCPUs
>   xen/riscv: introduce vCPU AIA initialization
>   xen/riscv: add IMSIC state save/restore
>   xen/riscv: add helper to check APLIC MSI mode
>   xen/riscv: introduce vintc_state_{save,restore}()
>   xen/riscv: add vAPLIC state save/restore hooks
>   xen/riscv: extend exception tables with type and data fields
>   xen/riscv: add unprivileged guest memory read helper
>   xen/riscv: add guest page fault handling stub
>   xen/riscv: implement trap redirection to a guest
>   xen/riscv: add guest load emulation for trapped MMIO accesses
>   xen/riscv: add guest store emulation for trapped MMIO accesses

Where did the last two patches go? My inbox agrees with [1] that only 15 of the
17 patches arrived.

Jan

[1] https://lists.xen.org/archives/html/xen-devel/2026-07/threads.html



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.