[PATCH 2.5/5] x86/nmi: Remove logic for pre-64bit Pentium 4 CPUs

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

Model 3 was the first 64bit-capable P4.  Xen won't be booting on anything
older, so remove the condition.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <jbeulich@xxxxxxxx>
CC: Roger Pau Monné <roger@xxxxxxxxxxxxxx>
CC: Teddy Astie <teddy.astie@xxxxxxxxxx>
---
 xen/arch/x86/nmi.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c
index b71bf4363586..d614641386c7 100644
--- a/xen/arch/x86/nmi.c
+++ b/xen/arch/x86/nmi.c
@@ -314,13 +314,9 @@ static void setup_p4_watchdog(void)
         clear_msr_range(0x3F1, 2);
     /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
        docs doesn't fully define it, so leave it alone for now. */
-    if (boot_cpu_data.model >= 0x3) {
-        /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
-        clear_msr_range(0x3A0, 26);
-        clear_msr_range(0x3BC, 3);
-    } else {
-        clear_msr_range(0x3A0, 31);
-    }
+    /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
+    clear_msr_range(0x3A0, 26);
+    clear_msr_range(0x3BC, 3);
     clear_msr_range(0x3C0, 6);
     clear_msr_range(0x3C8, 6);
     clear_msr_range(0x3E0, 2);
-- 
2.39.5