RE: [Xen-ia64-devel] SMP-g status.

["Yang, Fred" <fred.yang@xxxxxxxxx>]

>-----Original Message-----
>From: xen-ia64-devel-bounces@xxxxxxxxxxxxxxxxxxx 
>[mailto:xen-ia64-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf 
>Of Magenheimer, Dan (HP Labs Fort Collins)
>Sent: Wednesday, April 26, 2006 1:46 PM
>To: Tristan Gingold; xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
>Subject: RE: [Xen-ia64-devel] SMP-g status.
>
>> From: Tristan Gingold [mailto:Tristan.Gingold@xxxxxxxx] 
>> Sent: Wednesday, April 26, 2006 1:33 AM
>> To: Magenheimer, Dan (HP Labs Fort Collins); 
>> xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
>> Subject: Re: [Xen-ia64-devel] SMP-g status.
>> 
>> Le Mardi 25 Avril 2006 18:43, Magenheimer, Dan (HP Labs Fort 
>> Collins) a écrit 
>> :
>> > Wow!  Amazing work, Tristan!
>> >
>> > Is this a 4-socket "future processor" with 2 cores
>> > and 2 threads on each core?
>> Yes, 4 montecito with 4 threads.
>> 
>> >  I wonder if the threading
>> > mechanism on this processor differs sufficiently
>> > from hyperthreading on x86 that Xen/ia64 might need
>> > to deal differently with threads?
>> What do you mean by to deal ?
>
>There are many different ways of architecting hyperthreading.
>Some may be better suited for one software implementation
>than another.  Saying anything further would probably
>be inappropriate so would have to wait until chips are
>available publicly.
>
Multi-threading shares pipeline and cache within a core.  Xen/IA64 has 
separated RID set for each domain, allocating new domain base on per core 
scheduling may be a better approach for start

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