[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-users] Xen Security Advisory 263 (CVE-2018-3639) - Speculative Store Bypass
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2018-3639 / XSA-263 Speculative Store Bypass ISSUE DESCRIPTION ================= Contemporary high performance processors may use a technique commonly known as Memory Disambiguation, whereby speculative execution may proceed past unresolved stores. This opens a speculative sidechannel in which loads from an address which have had a recent store can observe and operate on the older, stale, value. For more details, see: https://bugs.chromium.org/p/project-zero/issues/detail?id=1528 https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00115.html https://www.amd.com/securityupdates IMPACT ====== An attacker who can locate or create a suitable code gadget in a different privilege context may be able to infer the content of arbitrary memory accessible to that other privilege context. At the time of writing, there are no known vulnerable gadgets in the compiled hypervisor code. Xen has no interfaces which allow JIT code to be provided. Therefore we believe that the hypervisor itself is not vulnerable. Additionally, we do not think there is a viable information leak by one Xen guest against another non-cooperating guest. However, in most configurations, within-guest information leak is possible. Mitigation for this generally depends on guest changes (for which you must consult your OS vendor) *and* on hypervisor support, provided in this advisory. VULNERABLE SYSTEMS ================== Systems running all versions of Xen are affected. Processors from all vendors are affected to different extents. Further communication will be made for Arm. See https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability for more details. MITIGATION ========== This issue can be mitigated with a combination of software and firmware changes. RESOLUTION ========== This is a hardware bug. The primary mitigation in Xen context is modification of guests, especially JITs in guests, to avoid generating vulnerable code. Such modifications do not require support from Xen. Alternatively, the following patches provide some workarounds: On AMD hardware, for Fam15h processors and later, the patches offer a host-wide global control for whether Memory Disambiguation is enabled (default) or disabled. Controls are not virtualised for guests. When the global control is set to disabled (`spec-ctrl=ssbd' on the hypervisor command line), the vulnerability is eliminated without the need for other guest or hypervisor changes. On Intel hardware, a microcode update is required in order to work around the problem by disabling memory disambiguation. Consult your hardware vendor or your dom0 OS distributor for the firmware/microcode update. With the microcode update in place, the patches offer a host-wide control (which would eliminate the vulnerability on the whole system without guest changes), and virtualised controls for guests to use (which addresses the issue in a guest-specific manner). Consult your guest operating system vendors, for further information and advice. (Additionally, host firmware may be vulnerable and may require updates for that reason. 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xsa263-4.8/0014-x86-msr-Virtualise-MSR_SPEC_CTRL.SSBD-for-guests-to-.patch Attachment:
xsa263-4.9/0001-x86-spec_ctrl-Read-MSR_ARCH_CAPABILITIES-only-once.patch Attachment:
xsa263-4.9/0002-x86-spec_ctrl-Express-Xen-s-choice-of-MSR_SPEC_CTRL-.patch Attachment:
xsa263-4.9/0003-x86-spec_ctrl-Merge-bti_ist_info-and-use_shadow_spec.patch Attachment:
xsa263-4.9/0004-x86-spec_ctrl-Fold-the-XEN_IBRS_-SET-CLEAR-ALTERNATI.patch Attachment:
xsa263-4.9/0005-x86-spec_ctrl-Rename-bits-of-infrastructure-to-avoid.patch Attachment:
xsa263-4.9/0006-x86-spec_ctrl-Elide-MSR_SPEC_CTRL-handling-in-idle-c.patch Attachment:
xsa263-4.9/0007-x86-spec_ctrl-Split-X86_FEATURE_SC_MSR-into-PV-and-H.patch Attachment:
xsa263-4.9/0008-x86-spec_ctrl-Explicitly-set-Xen-s-default-MSR_SPEC_.patch Attachment:
xsa263-4.9/0009-x86-cpuid-Improvements-to-guest-policies-for-specula.patch Attachment:
xsa263-4.9/0010-x86-spec_ctrl-Introduce-a-new-spec-ctrl-command-line.patch Attachment:
xsa263-4.9/0011-x86-AMD-Mitigations-for-GPZ-SP4-Speculative-Store-By.patch Attachment:
xsa263-4.9/0012-x86-Intel-Mitigations-for-GPZ-SP4-Speculative-Store-.patch Attachment:
xsa263-4.9/0013-x86-msr-Virtualise-MSR_SPEC_CTRL.SSBD-for-guests-to-.patch Attachment:
xsa263-4.10/0001-x86-spec_ctrl-Read-MSR_ARCH_CAPABILITIES-only-once.patch Attachment:
xsa263-4.10/0002-x86-spec_ctrl-Express-Xen-s-choice-of-MSR_SPEC_CTRL-.patch Attachment:
xsa263-4.10/0003-x86-spec_ctrl-Merge-bti_ist_info-and-use_shadow_spec.patch Attachment:
xsa263-4.10/0004-x86-spec_ctrl-Fold-the-XEN_IBRS_-SET-CLEAR-ALTERNATI.patch Attachment:
xsa263-4.10/0005-x86-spec_ctrl-Rename-bits-of-infrastructure-to-avoid.patch Attachment:
xsa263-4.10/0006-x86-spec_ctrl-Elide-MSR_SPEC_CTRL-handling-in-idle-c.patch Attachment:
xsa263-4.10/0007-x86-spec_ctrl-Split-X86_FEATURE_SC_MSR-into-PV-and-H.patch Attachment:
xsa263-4.10/0008-x86-spec_ctrl-Explicitly-set-Xen-s-default-MSR_SPEC_.patch Attachment:
xsa263-4.10/0009-x86-cpuid-Improvements-to-guest-policies-for-specula.patch Attachment:
xsa263-4.10/0010-x86-spec_ctrl-Introduce-a-new-spec-ctrl-command-line.patch Attachment:
xsa263-4.10/0011-x86-AMD-Mitigations-for-GPZ-SP4-Speculative-Store-By.patch Attachment:
xsa263-4.10/0012-x86-Intel-Mitigations-for-GPZ-SP4-Speculative-Store-.patch Attachment:
xsa263-4.10/0013-x86-msr-Virtualise-MSR_SPEC_CTRL.SSBD-for-guests-to-.patch _______________________________________________ Xen-users mailing list Xen-users@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-users
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