[Xen-changelog] [xen-unstable] X86: expose HLE/RTM features to dom0

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Liu, Jinsong <jinsong.liu@xxxxxxxxx>
# Date 1330416387 -3600
# Node ID 72551f5787763afe1c71f7f7e3999c4c2cbdd26f
# Parent  a7bacdc5449a2f7bb9c35b2a1334b463fe9f29a9
X86: expose HLE/RTM features to dom0

Intel recently release 2 new features, HLE and TRM.
Refer to http://software.intel.com/file/41417.
This patch expose them to dom0.

Signed-off-by: Liu, Jinsong <jinsong.liu@xxxxxxxxx>
Committed-by: Jan Beulich <jbeulich@xxxxxxxx>
---


diff -r a7bacdc5449a -r 72551f578776 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Mon Feb 27 17:05:18 2012 +0000
+++ b/xen/arch/x86/traps.c      Tue Feb 28 09:06:27 2012 +0100
@@ -857,9 +857,11 @@
     case 0x00000007:
         if ( regs->ecx == 0 )
             b &= (cpufeat_mask(X86_FEATURE_BMI1) |
+                  cpufeat_mask(X86_FEATURE_HLE)  |
                   cpufeat_mask(X86_FEATURE_AVX2) |
                   cpufeat_mask(X86_FEATURE_BMI2) |
                   cpufeat_mask(X86_FEATURE_ERMS) |
+                  cpufeat_mask(X86_FEATURE_RTM)  |
                   cpufeat_mask(X86_FEATURE_FSGSBASE));
         else
             b = 0;
diff -r a7bacdc5449a -r 72551f578776 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h  Mon Feb 27 17:05:18 2012 +0000
+++ b/xen/include/asm-x86/cpufeature.h  Tue Feb 28 09:06:27 2012 +0100
@@ -149,11 +149,13 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
 #define X86_FEATURE_FSGSBASE   (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_BMI1       (7*32+ 3) /* 1st bit manipulation extensions */
+#define X86_FEATURE_HLE        (7*32+ 4) /* Hardware Lock Elision */
 #define X86_FEATURE_AVX2       (7*32+ 5) /* AVX2 instructions */
 #define X86_FEATURE_SMEP       (7*32+ 7) /* Supervisor Mode Execution 
Protection */
 #define X86_FEATURE_BMI2       (7*32+ 8) /* 2nd bit manipulation extensions */
 #define X86_FEATURE_ERMS       (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
 #define X86_FEATURE_INVPCID    (7*32+10) /* Invalidate Process Context ID */
+#define X86_FEATURE_RTM        (7*32+11) /* Restricted Transactional Memory */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)

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