[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen master] arm64: ITS: fix cacheability adjustment
commit 31309b538f77a9eac5b9d1308335612ebd96bd3d Author: Andre Przywara <andre.przywara@xxxxxxxxxx> AuthorDate: Thu Nov 16 12:02:35 2017 +0000 Commit: Stefano Stabellini <sstabellini@xxxxxxxxxx> CommitDate: Tue Nov 28 11:27:13 2017 -0800 arm64: ITS: fix cacheability adjustment If the host GICv3 redistributor reports that the pending table cannot use shareable memory, we try to drop the cacheability attributes as well. However we fail horribly in doing computer science 101 bit masking, effectively clearing the whole register instead of just a few bits. Fix this by removing the one redundant masking operation and adding the magic negation for the actually needed other operation. Reported-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxxxxx> Reviewed-by: Julien Grall <julien.grall@xxxxxxxxxx> Release-Acked-by: Julien Grall <julien.grall@xxxxxxxxxx> --- xen/arch/arm/gic-v3-lpi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index c3474f5..8458215 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -359,8 +359,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base) /* If the hardware reports non-shareable, drop cacheability as well. */ if ( !(table_reg & GICR_PENDBASER_SHAREABILITY_MASK) ) { - table_reg &= GICR_PENDBASER_SHAREABILITY_MASK; - table_reg &= GICR_PENDBASER_INNER_CACHEABILITY_MASK; + table_reg &= ~GICR_PENDBASER_INNER_CACHEABILITY_MASK; table_reg |= GIC_BASER_CACHE_nC << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT; writeq_relaxed(table_reg, rdist_base + GICR_PENDBASER); -- generated by git-patchbot for /home/xen/git/xen.git#master _______________________________________________ Xen-changelog mailing list Xen-changelog@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/xen-changelog
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