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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen master] x86: move domain_cpu_policy_changed()
commit 46a5f4fb5a973b10809d6d5438c1ddb419de5496
Author: Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Wed Aug 19 11:08:46 2020 +0200
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Aug 19 11:08:46 2020 +0200
x86: move domain_cpu_policy_changed()
This is in preparation of making the building of domctl.c conditional.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
xen/arch/x86/domain.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++++++
xen/arch/x86/domctl.c | 167 --------------------------------------------------
2 files changed, 167 insertions(+), 167 deletions(-)
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index d1ecc7b83b..00ef05b4af 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -294,6 +294,173 @@ void update_guest_memory_policy(struct vcpu *v,
}
}
+void domain_cpu_policy_changed(struct domain *d)
+{
+ const struct cpuid_policy *p = d->arch.cpuid;
+ struct vcpu *v;
+
+ if ( is_pv_domain(d) )
+ {
+ if ( ((levelling_caps & LCAP_1cd) == LCAP_1cd) )
+ {
+ uint64_t mask = cpuidmask_defaults._1cd;
+ uint32_t ecx = p->basic._1c;
+ uint32_t edx = p->basic._1d;
+
+ /*
+ * Must expose hosts HTT and X2APIC value so a guest using native
+ * CPUID can correctly interpret other leaves which cannot be
+ * masked.
+ */
+ if ( cpu_has_x2apic )
+ ecx |= cpufeat_mask(X86_FEATURE_X2APIC);
+ if ( cpu_has_htt )
+ edx |= cpufeat_mask(X86_FEATURE_HTT);
+
+ switch ( boot_cpu_data.x86_vendor )
+ {
+ case X86_VENDOR_INTEL:
+ /*
+ * Intel masking MSRs are documented as AND masks.
+ * Experimentally, they are applied after OSXSAVE and APIC
+ * are fast-forwarded from real hardware state.
+ */
+ mask &= ((uint64_t)edx << 32) | ecx;
+
+ if ( ecx & cpufeat_mask(X86_FEATURE_XSAVE) )
+ ecx = cpufeat_mask(X86_FEATURE_OSXSAVE);
+ else
+ ecx = 0;
+ edx = cpufeat_mask(X86_FEATURE_APIC);
+
+ mask |= ((uint64_t)edx << 32) | ecx;
+ break;
+
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
+ mask &= ((uint64_t)ecx << 32) | edx;
+
+ /*
+ * AMD masking MSRs are documented as overrides.
+ * Experimentally, fast-forwarding of the OSXSAVE and APIC
+ * bits from real hardware state only occurs if the MSR has
+ * the respective bits set.
+ */
+ if ( ecx & cpufeat_mask(X86_FEATURE_XSAVE) )
+ ecx = cpufeat_mask(X86_FEATURE_OSXSAVE);
+ else
+ ecx = 0;
+ edx = cpufeat_mask(X86_FEATURE_APIC);
+
+ /*
+ * If the Hypervisor bit is set in the policy, we can also
+ * forward it into real CPUID.
+ */
+ if ( p->basic.hypervisor )
+ ecx |= cpufeat_mask(X86_FEATURE_HYPERVISOR);
+
+ mask |= ((uint64_t)ecx << 32) | edx;
+ break;
+ }
+
+ d->arch.pv.cpuidmasks->_1cd = mask;
+ }
+
+ if ( ((levelling_caps & LCAP_6c) == LCAP_6c) )
+ {
+ uint64_t mask = cpuidmask_defaults._6c;
+
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ mask &= (~0ULL << 32) | p->basic.raw[6].c;
+
+ d->arch.pv.cpuidmasks->_6c = mask;
+ }
+
+ if ( ((levelling_caps & LCAP_7ab0) == LCAP_7ab0) )
+ {
+ uint64_t mask = cpuidmask_defaults._7ab0;
+
+ /*
+ * Leaf 7[0].eax is max_subleaf, not a feature mask. Take it
+ * wholesale from the policy, but clamp the features in 7[0].ebx
+ * per usual.
+ */
+ if ( boot_cpu_data.x86_vendor &
+ (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
+ mask = (((uint64_t)p->feat.max_subleaf << 32) |
+ ((uint32_t)mask & p->feat._7b0));
+
+ d->arch.pv.cpuidmasks->_7ab0 = mask;
+ }
+
+ if ( ((levelling_caps & LCAP_Da1) == LCAP_Da1) )
+ {
+ uint64_t mask = cpuidmask_defaults.Da1;
+ uint32_t eax = p->xstate.Da1;
+
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ mask &= (~0ULL << 32) | eax;
+
+ d->arch.pv.cpuidmasks->Da1 = mask;
+ }
+
+ if ( ((levelling_caps & LCAP_e1cd) == LCAP_e1cd) )
+ {
+ uint64_t mask = cpuidmask_defaults.e1cd;
+ uint32_t ecx = p->extd.e1c;
+ uint32_t edx = p->extd.e1d;
+
+ /*
+ * Must expose hosts CMP_LEGACY value so a guest using native
+ * CPUID can correctly interpret other leaves which cannot be
+ * masked.
+ */
+ if ( cpu_has_cmp_legacy )
+ ecx |= cpufeat_mask(X86_FEATURE_CMP_LEGACY);
+
+ /*
+ * If not emulating AMD or Hygon, clear the duplicated features
+ * in e1d.
+ */
+ if ( !(p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
+ edx &= ~CPUID_COMMON_1D_FEATURES;
+
+ switch ( boot_cpu_data.x86_vendor )
+ {
+ case X86_VENDOR_INTEL:
+ mask &= ((uint64_t)edx << 32) | ecx;
+ break;
+
+ case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
+ mask &= ((uint64_t)ecx << 32) | edx;
+
+ /*
+ * Fast-forward bits - Must be set in the masking MSR for
+ * fast-forwarding to occur in hardware.
+ */
+ ecx = 0;
+ edx = cpufeat_mask(X86_FEATURE_APIC);
+
+ mask |= ((uint64_t)ecx << 32) | edx;
+ break;
+ }
+
+ d->arch.pv.cpuidmasks->e1cd = mask;
+ }
+ }
+
+ for_each_vcpu ( d, v )
+ {
+ cpuid_policy_updated(v);
+
+ /* If PMU version is zero then the guest doesn't have VPMU */
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+ p->basic.pmu_version == 0 )
+ vpmu_destroy(v);
+ }
+}
+
#ifndef CONFIG_BIGMEM
/*
* The hole may be at or above the 44-bit boundary, so we need to determine
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 6f2c69788d..7c644add92 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -49,173 +49,6 @@ static int gdbsx_guest_mem_io(domid_t domid, struct
xen_domctl_gdbsx_memio *iop)
}
#endif
-void domain_cpu_policy_changed(struct domain *d)
-{
- const struct cpuid_policy *p = d->arch.cpuid;
- struct vcpu *v;
-
- if ( is_pv_domain(d) )
- {
- if ( ((levelling_caps & LCAP_1cd) == LCAP_1cd) )
- {
- uint64_t mask = cpuidmask_defaults._1cd;
- uint32_t ecx = p->basic._1c;
- uint32_t edx = p->basic._1d;
-
- /*
- * Must expose hosts HTT and X2APIC value so a guest using native
- * CPUID can correctly interpret other leaves which cannot be
- * masked.
- */
- if ( cpu_has_x2apic )
- ecx |= cpufeat_mask(X86_FEATURE_X2APIC);
- if ( cpu_has_htt )
- edx |= cpufeat_mask(X86_FEATURE_HTT);
-
- switch ( boot_cpu_data.x86_vendor )
- {
- case X86_VENDOR_INTEL:
- /*
- * Intel masking MSRs are documented as AND masks.
- * Experimentally, they are applied after OSXSAVE and APIC
- * are fast-forwarded from real hardware state.
- */
- mask &= ((uint64_t)edx << 32) | ecx;
-
- if ( ecx & cpufeat_mask(X86_FEATURE_XSAVE) )
- ecx = cpufeat_mask(X86_FEATURE_OSXSAVE);
- else
- ecx = 0;
- edx = cpufeat_mask(X86_FEATURE_APIC);
-
- mask |= ((uint64_t)edx << 32) | ecx;
- break;
-
- case X86_VENDOR_AMD:
- case X86_VENDOR_HYGON:
- mask &= ((uint64_t)ecx << 32) | edx;
-
- /*
- * AMD masking MSRs are documented as overrides.
- * Experimentally, fast-forwarding of the OSXSAVE and APIC
- * bits from real hardware state only occurs if the MSR has
- * the respective bits set.
- */
- if ( ecx & cpufeat_mask(X86_FEATURE_XSAVE) )
- ecx = cpufeat_mask(X86_FEATURE_OSXSAVE);
- else
- ecx = 0;
- edx = cpufeat_mask(X86_FEATURE_APIC);
-
- /*
- * If the Hypervisor bit is set in the policy, we can also
- * forward it into real CPUID.
- */
- if ( p->basic.hypervisor )
- ecx |= cpufeat_mask(X86_FEATURE_HYPERVISOR);
-
- mask |= ((uint64_t)ecx << 32) | edx;
- break;
- }
-
- d->arch.pv.cpuidmasks->_1cd = mask;
- }
-
- if ( ((levelling_caps & LCAP_6c) == LCAP_6c) )
- {
- uint64_t mask = cpuidmask_defaults._6c;
-
- if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
- mask &= (~0ULL << 32) | p->basic.raw[6].c;
-
- d->arch.pv.cpuidmasks->_6c = mask;
- }
-
- if ( ((levelling_caps & LCAP_7ab0) == LCAP_7ab0) )
- {
- uint64_t mask = cpuidmask_defaults._7ab0;
-
- /*
- * Leaf 7[0].eax is max_subleaf, not a feature mask. Take it
- * wholesale from the policy, but clamp the features in 7[0].ebx
- * per usual.
- */
- if ( boot_cpu_data.x86_vendor &
- (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
- mask = (((uint64_t)p->feat.max_subleaf << 32) |
- ((uint32_t)mask & p->feat._7b0));
-
- d->arch.pv.cpuidmasks->_7ab0 = mask;
- }
-
- if ( ((levelling_caps & LCAP_Da1) == LCAP_Da1) )
- {
- uint64_t mask = cpuidmask_defaults.Da1;
- uint32_t eax = p->xstate.Da1;
-
- if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
- mask &= (~0ULL << 32) | eax;
-
- d->arch.pv.cpuidmasks->Da1 = mask;
- }
-
- if ( ((levelling_caps & LCAP_e1cd) == LCAP_e1cd) )
- {
- uint64_t mask = cpuidmask_defaults.e1cd;
- uint32_t ecx = p->extd.e1c;
- uint32_t edx = p->extd.e1d;
-
- /*
- * Must expose hosts CMP_LEGACY value so a guest using native
- * CPUID can correctly interpret other leaves which cannot be
- * masked.
- */
- if ( cpu_has_cmp_legacy )
- ecx |= cpufeat_mask(X86_FEATURE_CMP_LEGACY);
-
- /*
- * If not emulating AMD or Hygon, clear the duplicated features
- * in e1d.
- */
- if ( !(p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
- edx &= ~CPUID_COMMON_1D_FEATURES;
-
- switch ( boot_cpu_data.x86_vendor )
- {
- case X86_VENDOR_INTEL:
- mask &= ((uint64_t)edx << 32) | ecx;
- break;
-
- case X86_VENDOR_AMD:
- case X86_VENDOR_HYGON:
- mask &= ((uint64_t)ecx << 32) | edx;
-
- /*
- * Fast-forward bits - Must be set in the masking MSR for
- * fast-forwarding to occur in hardware.
- */
- ecx = 0;
- edx = cpufeat_mask(X86_FEATURE_APIC);
-
- mask |= ((uint64_t)ecx << 32) | edx;
- break;
- }
-
- d->arch.pv.cpuidmasks->e1cd = mask;
- }
- }
-
- for_each_vcpu ( d, v )
- {
- cpuid_policy_updated(v);
-
- /* If PMU version is zero then the guest doesn't have VPMU */
- if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
- p->basic.pmu_version == 0 )
- vpmu_destroy(v);
- }
-}
-
static int update_domain_cpu_policy(struct domain *d,
xen_domctl_cpu_policy_t *xdpc)
{
--
generated by git-patchbot for /home/xen/git/xen.git#master
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