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Re: [XenPPC] Re: IRQs delivery.

On Mar 10, 2006, at 12:00 PM, Olof Johansson wrote:

On Fri, Mar 10, 2006 at 09:30:38AM -0600, Hollis Blanchard wrote:

The IBM Research hypervisor (rhype) virtualized the PIC, so that instead of querying hardware, the kernel makes an hcall to find the incoming vector. If the interrupt is not in fact for this domain, the hypervisor queues the interrupt for later and tells the current domain "nothing was pending after all". Note that in this model, interrupts are delivered by the hardware
directly to the current domain without hypervisor involvement.

Actually rHype and xen configure the processor to deliver external interrupts directly to the hypervisor.

Not that you have a choice on PPC970,

This _is_ the case for 970 as well (it was not the case for POWER4).

but there's a drawback to this: If
you let all interrupts be delivered directly to the domain, then it can
hold the PIC "hostage" by disabling the delivery (keeping MSR_EE off),
causing interrupts to other domains to be delayed.

The Hostage (MSR_EE) bit problem exists does exist with 970.

Some PPC processors have a feature called "mediated external interrupts",
where they will be delivered to the hypervisor instead,

MEI does not make this descision.. the LPES does.
The problem MEI solves (as you mention below) is the case that the HV wants to deliver an interrupt but MSR_EE for the domain is off. MEI allows the hypervisor to force the processor a special form of external when the domain sets MSR_EE.

and if the domain
can't service it then (MSR_EE off), the HV can request to be notified
when the domain can take it. The extra code path for re-delivering to a
domain can be made short.

rHype has some support for this already, but it's unclear which hardware
has it. If I had to guess I would say at least Cell, since those parts
of rhype are ripped out in the sources but some of the infrastructure
is still in there.
Yes it is for Cell and other forth-comming processors. It is really for latency issues of RTOS (and games), server workloads are not expected to ever need this.

I'm just mentioning this in case the IA64 guys have something like
mediated interrupts as an option, they might want to go with that for
the fairness/latency reasons.

Does IA64 indeed have MEI like abilities or the ability to route the interrupt?

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