[Xen-devel] [PATCH] vlapic.c - TDCR

[Ben Thomas <bthomas@xxxxxxxxxxxxxxx>]

Clean up two small APIC TDCR issues.  First, only save the bits that
can be set, so that a subsequent read can't see MBZ bits as set.
Next, be sure to initialize the timer_divide_count, which is derived
from the TDCR.  This avoids a potential divide-by-zero elsewhere in the
code.  Technically, the timer_divide_count initialization should be done
from the value of the TDCR, but it's in the init routine and the
registers were all just zeroed by the caller of the init routine.


Signed-off-by: Ben Thomas (ben@xxxxxxxxxxxxxxx)
--
------------------------------------------------------------------------
Ben Thomas                                         Virtual Iron Software
bthomas@xxxxxxxxxxxxxxx                            Tower 1, Floor 2
978-849-1214                                       900 Chelmsford Street
                                                   Lowell, MA 01851

# Clean up two small APIC TDCR issues.  First, only save the bits that
# can be set, so that on a subsequent read can't see MBZ bits as set.
# Next, be sure to initialize the timer_divide_count, which is derived
# from the TDCR.  This avoids a potential divide-by-zero elsewhere in the
# code.  Technically, the timer_divide_count initialization should be done
# from the value of the TDCR, but it's in the init routine and the
# registers were all just zeroed.
#
# Signed-off-by: Ben Thomas (ben@xxxxxxxxxxxxxxx)

Index: xen-unstable.hg/xen/arch/x86/hvm/vlapic.c
===================================================================
--- xen-unstable.hg.orig/xen/arch/x86/hvm/vlapic.c      2006-11-08 
17:06:11.000000000 -0500
+++ xen-unstable.hg/xen/arch/x86/hvm/vlapic.c   2006-11-08 17:07:55.000000000 
-0500
@@ -779,11 +779,11 @@
     {
         unsigned int tmp1, tmp2;
 
-        tmp1 = val & 0xf;
+        tmp1 = val & 0xb;              /* Only bits 0,1,3 are settable */
         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
         vlapic->timer_divide_count = 0x1 << (tmp2 & 0x7);
 
-        vlapic_set_reg(vlapic, APIC_TDCR, val);
+        vlapic_set_reg(vlapic, APIC_TDCR, tmp1);
 
         HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "timer divide count is 0x%x",
                     vlapic->timer_divide_count);
@@ -966,6 +966,7 @@
     vlapic->apic_base_msr = MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
 
     vlapic->flush_tpr_threshold = 0;
+    vlapic->timer_divide_count = 2;    /* TDCR of 0, means divide by 2 */
 
     vlapic->base_address = vlapic->apic_base_msr &
                            MSR_IA32_APICBASE_BASE;

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