[Xen-devel] RE: A question about PIT platform timer

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

>From: Keir Fraser [mailto:keir@xxxxxxxxxxxxx]
>Sent: 2006年12月11日 17:36
>On 11/12/06 09:05, "Tian, Kevin" <kevin.tian@xxxxxxxxx> wrote:
>
>> Just note that pit_read_counter is implemented on top of CH2 of PIT,
>> which is known as mode 0 to calibrate TSC earlier. However I see no
>> place to re-initialize it again and it's used as the source of platform
>> timer count (when using_pit==1) immediately. It seems like weird
>> usage since mode0 channel will fall into a loop starting counting down
>> from 0xFFFF forever if nobody re-latches it again, which indicates a
>> 18.2065 Hz source while platform_timer_scale is set as
>CLOCK_TICK_RATE.
>>
>> Seems ch0 is what's really wanted... Is it a typo, or any special usage
>> on ch2?
>
>We use it as a free-running globally-accessible counter of known
>frequency.
>We don't take interrupts from it (in fact we can't even if we wanted to as
>it's not wired up to an IRQ).
>
> -- Keir

Yes, there's no interrupt from it. But what's the known frequency? 
CALIBRATE_LATCH or CLOCK_TICK_RATE? platform_timer_scale 
is set to the later, and so ch2 needs to work on same frequency or 
else count value will result incorrect offset. However I didn't see such 
setting on ch2. Does I miss something? :-)

Thanks,
Kevin

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