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[Xen-devel] x86 Physical CPUs at different frequencies - timer error messages

  • To: xen-devel@xxxxxxxxxxxxxxxxxxx
  • From: "Langsdorf, Mark" <mark.langsdorf@xxxxxxx>
  • Date: Wed, 21 Mar 2007 16:15:56 -0500
  • Delivery-date: Wed, 21 Mar 2007 14:17:16 -0700
  • List-id: Xen developer discussion <xen-devel.lists.xensource.com>
  • Thread-index: Acdr/h2lJYOLuG6hSmOdfezIox4rPw==
  • Thread-topic: x86 Physical CPUs at different frequencies - timer error messages

I'm experimenting with getting PowerNow! running on
SMP Opteron systems.  

One problem I'm having is that Xen assumes that all
physical processors are incrementing the TSCs at 
the same rate, and complains in the timer ISR that
time is going backward if this isn't the case:

"Timer ISR/1: Time went backwards: delta=BIGNUM1
delta_cpu=BIGNUM2 shadow=BIGNUM3 off=BIGNUM4
processed=BIGNUM5 cpu_processed=BIGNUM6
 1: BIGNUM6"

I'm not surprised this is happening, since the TSC
values on processor 0 and processor 1 increment at
different rates and tend to have wildly differing
values.  Normally AMD strongly discourages using 
TSC for time-keeping with PowerNow! enabled for 
exactly this reason.

However, the worst effects of time skew that we
see on native systems is not happening on my dom0
with PowerNow!.  How much should I worry about this
and what can be done to mitigate it?

-Mark Langsdorf
AMD, Inc.

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