RE: [Xen-devel] x86 Physical CPUs at different frequencies - timer error messages

["Ian Pratt" <Ian.Pratt@xxxxxxxxxxxx>]

> I'm experimenting with getting PowerNow! running on
> SMP Opteron systems.
> 
> One problem I'm having is that Xen assumes that all
> physical processors are incrementing the TSCs at
> the same rate, and complains in the timer ISR that
> time is going backward if this isn't the case:

Xen *is* able to cope with TSCs running at different frequencies. It
calibrates each CPU every few seconds on the assumption that the
frequencies are basically stable but different. 

To integrate with PowerNow, after you've changed the frequency you need
to run the code to generate a new time record and propagate it to the
VCPU of the guest currently using the CPU. For the frequency field, you
are best off scaling the frequency measured in the last calibration
period rather than assuming the new target frequency is precise.

Ian

> "Timer ISR/1: Time went backwards: delta=BIGNUM1
> delta_cpu=BIGNUM2 shadow=BIGNUM3 off=BIGNUM4
> processed=BIGNUM5 cpu_processed=BIGNUM6
>  0: BIGNUM5
>  1: BIGNUM6"
> 
> I'm not surprised this is happening, since the TSC
> values on processor 0 and processor 1 increment at
> different rates and tend to have wildly differing
> values.  Normally AMD strongly discourages using
> TSC for time-keeping with PowerNow! enabled for
> exactly this reason.
> 
> However, the worst effects of time skew that we
> see on native systems is not happening on my dom0
> with PowerNow!.  How much should I worry about this
> and what can be done to mitigate it?
> 
> -Mark Langsdorf
> AMD, Inc.
> 
> 
> 
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