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RE: [Xen-devel] Question about implementation of 32-bit guestson64-bit hypervisor (IDT-related)

Keir Fraser wrote:
> On 7/12/07 22:06, "Keir Fraser" <Keir.Fraser@xxxxxxxxxxxx> wrote:
> > Yes. I believe that the Intel manuals are incorrect in stating that
> > pagetables are restricted to 36-bit addressing. Processors which
> > long mode have their physical address size advertised in CPUID, and
> > pretty sure that addresses up to that size can be poked into 8-byte
> > pagetable entries whether the pagetable format is 64-bit-mode or
> > AMD state explicitly in their manual that PAE pagetables can address
up to
> > 52 bits, just like 64-bit pagetables, and that this is the
> > limit. Furthermore, you guys (Unisys) have done testing on big
memory ES7000
> > systems (>128GB), and those are Intel boxes -- and I expect some of
> > testing has been 32-bit HVM guests? Given we allocate larger
> > first, this would confirm that Intel really does allow addresses
>64GB in
> > PAE pagetables in practice.
> Although Intel SDM Vol 3A Section 3.8 makes it look like PAE only
> 36-bit addressing, the manual simply hasn't been updated properly.
There are
> various references elsewhere in Vol 3 that make it clear that PAE
> is extended on Intel64 processors that have more address lines. The
> statement I can find is the second footnote of Section in Vol
> (the latest Vol 3B, dated Nov 2007). I'm glad Intel don't hide these
> away. ;-)

You should be able to find this in SDM Vol 3A:
3.8.1 Enhanced Legacy PAE Paging
On Intel 64 processors, the page directory pointer entry supports
physical address size of the underlying implementation (reported by
CPUID.80000008H). Legacy PAE enabled paging [see Section 3.8.2, "Linear
Address Translation With PAE Enabled (4-KByte Pages)" and Section 3.8.3,
"Linear Address Translation With PAE Enabled (2-MByte Pages)"] can
address physical memory greater than 64-GByte if the implementation's
physical address size is greater than 36 bits.

>  -- Keir

Intel Open Source Technology Center

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