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Re: [Xen-devel] Question about implementation of 32-bit guestson64-bit hypervisor (IDT-related)

On 8/12/07 05:54, "Nakajima, Jun" <jun.nakajima@xxxxxxxxx> wrote:

> You should be able to find this in SDM Vol 3A:
> 3.8.1 Enhanced Legacy PAE Paging
> On Intel 64 processors, the page directory pointer entry supports
> physical address size of the underlying implementation (reported by
> CPUID.80000008H). Legacy PAE enabled paging [see Section 3.8.2, "Linear
> Address Translation With PAE Enabled (4-KByte Pages)" and Section 3.8.3,
> "Linear Address Translation With PAE Enabled (2-MByte Pages)"] can
> address physical memory greater than 64-GByte if the implementation's
> physical address size is greater than 36 bits.

Ah, I missed the most obvious one!

 -- Keir

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