Re: [Xen-devel] page table question!

[Tim Deegan <Tim.Deegan@xxxxxxxxxx>]

At 11:07 +0800 on 16 Dec (1197803269), tgh wrote:
> nested page table ,for the AMD NPT ,is stored in the dom0 linear space, 
> not in the hypervisor virtual address ,is it? or what is the meaning of 
> "that's one major benefit of nested paging: counteraction "address space 
> compression".",and what about the Intel EPT, is it similar ,or how does 
> it work, I am still comfused about the hypervisor' limited virtual 
> address space, it wont be used for storing the EPT or NPT, is it? or 
> what about  the hypervisor's virtual address space in the AMD or 
> Intel-vt?how much space is it? or what is tricks behind, could you give 
> me a more detailed explanation about NPT and EPT

NPT is described in volume 2 of AMD's Architecture Programmer's Manual.
http://www.amd.com/us-en/Processors/TechnicalResources/0,,30_182_739_7044,00.html

I don't know of any publically available documentation on EPT, but there
are some details in Jun Nakajima's slides from the recent Xen Summit.
http://xen.org/xensummit/xensummit_fall_2007.html

Tim.

-- 
Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Principal Software Engineer, Citrix Systems.
[Company #5334508: XenSource UK Ltd, reg'd c/o EC2Y 5EB, UK.]

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