Oh, I made some mistakes. I have just checked
PCI-e 1.1 spec. It seems the definition of this capability structure is
different with PCI-e 2.0. I will check more and find a solution.
From: Keir Fraser
[mailto:keir.fraser@xxxxxxxxxxxxx]
Sent: 2008年10月9日 17:03
To: Shan, Haitao; xen-devel@xxxxxxxxxxxxxxxxxxx
Cc: Jiang,
Yunhong; Li, Xin B;
Tian, Kevin; Huang, Zhiteng
Subject: Re: [Question] Do we need
to support devices that do not strictly follow the PCI-e specification?
On 9/10/08 09:28, "Shan, Haitao" <haitao.shan@xxxxxxxxx> wrote:
Hi, Keir,
When debugging recently, I found some devices that did not follow the PCI-e
specification strictly. Below is an example.
From PCI-e spec, PCI-e
capability occupies 0x3c bytes of configuration space. Unimplemented registers
are reserved and hardwired to zero. But for device listed below, PCI-e
capability should begin at 0x4C and end at 0x88. But this device implements
MSI, VPD, MSI-X capabilities in the reserved spaces. Current code can not
handle this.
My question is do we
need to add hacks to handle such kinds of devices?
I thought PCI capability offsets could be dynamically determined? If
so, or there are other means to easily determine actual capability offsets
without requiring explicit device-quirk lists, we should employ those means.
-- Keir
