[Xen-devel] [PATCH]: Let dom0 write to the APERF and MPERF MSR's

[Chris Lalancette <clalance@xxxxxxxxxx>]

All,
     If dom0 is controlling the frequency scaling (which it still is in RHEL-5),
and it's using the new acpi-cpufreq code from upstream (which it is in 5.3),
then it will attempt to wrmsr() to the MSR_IA32_APERF and MSR_IA32_MPERF MSR's
(to do performance measuring, I believe).  With the current hypervisor, this
results in a lot of:

(XEN) traps.c:1761:d0 Domain attempted WRMSR 00000000000000e8 from
00000029:d7ca940f to 00000000:00000000.

messages.  I believe it is safe to let the dom0 do this MSR write, so the
attached patch just allows the write to go through.  This eliminates the message
spam, and probably allows acpi-cpufreq work to a certain extent (although I have
not verified the latter).

The patch was generated and tested on a RHEL-5 (3.1-based) hypervisor, but
should apply with a little massaging to xen-unstable.

Signed-off-by: Chris Lalancette <clalance@xxxxxxxxxx>

diff -urp xen.orig/arch/x86/traps.c xen/arch/x86/traps.c
--- xen.orig/arch/x86/traps.c   2009-01-16 14:22:09.000000000 +0100
+++ xen/arch/x86/traps.c        2009-01-16 14:55:11.000000000 +0100
@@ -1751,6 +1751,12 @@ static int emulate_privileged_op(struct 
                  wrmsr_safe(regs->ecx, eax, edx) )
                 goto fail;
             break;
+       case MSR_IA32_MPERF:
+       case MSR_IA32_APERF:
+            if ( (cpufreq_controller != FREQCTL_dom0_kernel) ||
+                 wrmsr_safe(regs->ecx, eax, edx) )
+                goto fail;
+            break;
         default:
             if ( wrmsr_hypervisor_regs(regs->ecx, eax, edx) )
                 break;
diff -urp xen.orig/include/asm-x86/msr.h xen/include/asm-x86/msr.h
--- xen.orig/include/asm-x86/msr.h      2009-01-16 14:22:09.000000000 +0100
+++ xen/include/asm-x86/msr.h   2009-01-16 14:24:42.000000000 +0100
@@ -198,6 +198,9 @@ static inline void write_efer(u64 val)
 #define MSR_IA32_PERF_STATUS           0x198
 #define MSR_IA32_PERF_CTL              0x199
 
+#define MSR_IA32_MPERF                 0x000000e7
+#define MSR_IA32_APERF                 0x000000e8
+
 #define MSR_IA32_THERM_CONTROL         0x19a
 #define MSR_IA32_THERM_INTERRUPT       0x19b
 #define MSR_IA32_THERM_STATUS          0x19c

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