Re: [Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

[Haitao Shan <maillists.shan@xxxxxxxxx>]

Hi, Keir, Jan,

I will ACK to Jan's patch.
Concernng Jan's question, I am not sure whether the specific model is
NHM or SNB. But I can confirm they are all NHM/SNB. I think this is
not important to last branch record, though.

Shan Haitao

2011/10/4 Keir Fraser <keir@xxxxxxx>:
> On 04/10/2011 12:32, "Jan Beulich" <JBeulich@xxxxxxxx> wrote:
>
>> There are still a couple of family 6 models missing here: 37, 44, 46,
>> and 47 (according to SDM doc changes May 2011); presumably they would
>> all go into the Nehalem/Sandy Bridge group. Intel?
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>
> A nod or Ack from someone at Intel would be nice for this patch.
>
>  -- Keir
>
>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>> @@ -1693,6 +1693,20 @@ static const struct lbr_info {
>>      { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_C2_LASTBRANCH_FROM_TO },
>>      { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_C2_LASTBRANCH_FROM_TO },
>>      { 0, 0 }
>> +}, nh_lbr[] = {
>> +    { MSR_IA32_LASTINTFROMIP,       1 },
>> +    { MSR_IA32_LASTINTTOIP,         1 },
>> +    { MSR_C2_LASTBRANCH_TOS,        1 },
>> +    { MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
>> +    { MSR_P4_LASTBRANCH_0_TO_LIP,   NUM_MSR_P4_LASTBRANCH_FROM_TO },
>> +    { 0, 0 }
>> +}, at_lbr[] = {
>> +    { MSR_IA32_LASTINTFROMIP,       1 },
>> +    { MSR_IA32_LASTINTTOIP,         1 },
>> +    { MSR_C2_LASTBRANCH_TOS,        1 },
>> +    { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
>> +    { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
>> +    { 0, 0 }
>>  #ifdef __i386__
>>  }, pm_lbr[] = {
>>      { MSR_IA32_LASTINTFROMIP,       1 },
>> @@ -1720,8 +1734,20 @@ static const struct lbr_info *last_branc
>>  #endif
>>          /* Core2 Duo */
>>          case 15:
>> +        /* Enhanced Core */
>> +        case 23:
>>              return c2_lbr;
>>              break;
>> +        /* Nehalem */
>> +        case 26: case 30: case 31: case 46:
>> +        /* Sandy Bridge */
>> +        case 42: case 45:
>> +            return nh_lbr;
>> +            break;
>> +        /* Atom */
>> +        case 28:
>> +            return at_lbr;
>> +            break;
>>          }
>>          break;
>>
>> --- a/xen/include/asm-x86/msr-index.h
>> +++ b/xen/include/asm-x86/msr-index.h
>> @@ -472,11 +472,12 @@
>>  #define MSR_PM_LASTBRANCH_0  0x00000040
>>  #define NUM_MSR_PM_LASTBRANCH  8
>>
>> -/* Core 2 last-branch recording */
>> +/* Core 2 and Atom last-branch recording */
>>  #define MSR_C2_LASTBRANCH_TOS  0x000001c9
>>  #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040
>>  #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060
>>  #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
>> +#define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
>>
>>  /* Intel Core-based CPU performance counters */
>>  #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
>>
>>
>>
>>
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>
>
>
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