Re: [Xen-devel] Xen4.2 S3 regression?

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 27.09.12 at 14:12, Ben Guthro <ben@xxxxxxxxxx> wrote:
> On Thu, Sep 27, 2012 at 3:38 AM, Jan Beulich <JBeulich@xxxxxxxx> wrote:
>> > (XEN) microcode: collect_cpu_info for CPU0
>> > (XEN) microcode: collect_cpu_info : sig=0x10676, pf=0x80, rev=0x60c
>> > (XEN) microcode: collect_cpu_info for CPU1
>> > (XEN) microcode: collect_cpu_info : sig=0x10676, pf=0x80, rev=0x60f
>>
>> And in the end we see that both cores run on different revisions.
>>
>>
> very interesting. I had overlooked that.
> 
> 
>> The mixup of Xen and Dom0 messages puzzles me too - in my
>> understanding, all APs should be brought back up before
>> domains get unpaused. Is that perhaps part of your problem
>> with pinned vCPU-s? Or is the mixup not indicative of things
>> actually happening in parallel?
>>
> 
> It seems like it may be related, but I'm unsure how.
> When I run without the dom0_vcpu_pin option, I don't see the
> collect_cpu_info messages,
> nor do I see the microcode revision printout for CPU0

That's more likely because of either running different
(unpatched) code, or at a lower log level, because ...

> nor do I see the dom0 / Xen messages mised up.
> 
> [   41.567458] ACPI: Preparing to enter system sleep state S3
> [   42.020120] PM: Saving platform NVS memory
> [   42.092643] Disabling non-boot CPUs ...
> (XEN) Preparing system for ACPI S3 state.
> (XEN) Disabling non-boot CPUs ...
> (XEN) Entering ACPI S3 state.
> (XEN) mce_intel.c:1239: MCA Capability: BCAST 1 SER 0 CMCI 0 firstbank 1 
> extended MCE MSR 0
> (XEN) CMCI: CPU0 has no CMCI support
> (XEN) CPU0: Thermal monitoring enabled (TM2)
> (XEN) Finishing wakeup from ACPI S3 state.
> (XEN) Enabling non-boot CPUs  ...
> (XEN) Booting processor 1/1 eip 8a000
> (XEN) Initializing CPU#1
> (XEN) CPU: L1 I cache: 32K, L1 D cache: 32K
> (XEN) CPU: L2 cache: 3072K
> (XEN) CPU: Physical Processor ID: 0
> (XEN) CPU: Processor Core ID: 1
> (XEN) CMCI: CPU1 has no CMCI support
> (XEN) CPU1: Thermal monitoring enabled (TM2)
> (XEN) CPU1: Intel(R) Core(TM)2 Duo CPU     P8400  @ 2.26GHz stepping 06
> (XEN) microcode: CPU1 updated from revision 0x60c to 0x60f, date = 2010-09-29

... you can't get here without going through collect_cpu_info().

> [   42.200055] ACPI: Low-level resume complete
> [   42.200055] PM: Restoring platform NVS memory
> [   42.200055] Enabling non-boot CPUs ...
> 
> 
> Any pointers are appreciated.

Same for me (regarding the mixup of messages). Maybe widening
the console_{start,end}_sync() window from right after freezing
domains until right before thawing them could make clear whether
this is an artifact.

Jan


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