[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 1/2 v4] iommu/amd: Fix logic for clearing the IOMMU interrupt bits
On Mon, Jun 10, 2013 at 1:41 PM, Jan Beulich <JBeulich@xxxxxxxx> wrote: > The IOMMU interrupt bits in the IOMMU status registers are > "read-only, and write-1-to-clear (RW1C). Therefore, the existing > logic which reads the register, set the bit, and then writing back > the values could accidentally clear certain bits if it has been set. > > The correct logic would just be writing only the value which only > set the interrupt bits, and leave the rest to zeros. > > This patch also, clean up #define masks as Jan has suggested. > > Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx> > > With iommu_interrupt_handler() properly having got switched its readl() > from status to control register, the subsequent writel() needed to be > switched too (and the RW1C comment there was bogus). > > Some of the cleanup went too far - undone. > > Further, with iommu_interrupt_handler() now actually disabling the > interrupt sources, they also need to get re-enabled by the tasklet once > it finished processing the respective log. > > Finally, guest write emulation to the status register needs to be done > with the RW1C (and RO for all other bits) semantics in mind too. > > Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> What's the impact of this as a bug? This looks like it has a fairly high risk of introducing regressions in existing working system. So unless it has a pretty wide impact, I think we should wait and include this in 4.3.1. -George _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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