Re: [Xen-devel] [PATCH 1/4] xen/arm: introduce Cortex-A7 support

["Bamvor Jian Zhang" <bjzhang@xxxxxxxx>]

Ian Campbell wrote:
> On Fri, 2013-05-31 at 20:53 +0800, Bamvor Jian Zhang wrote:
>> diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
>> index 0588d54..d3b849b 100644
>> --- a/xen/arch/arm/arm32/head.S
>> +++ b/xen/arch/arm/arm32/head.S
>> @@ -20,6 +20,7 @@
>>  #include <asm/config.h>
>>  #include <asm/page.h>
>>  #include <asm/processor-ca15.h>
>> +#include <asm/processor-ca7.h>
>>  #include <asm/asm_defns.h>
>>  
>>  #define ZIMAGE_MAGIC_NUMBER 0x016f2818
>> @@ -195,8 +196,18 @@ skip_bss:
>>          /* Is this a Cortex A15? */
>>          ldr   r1, =(CORTEX_A15_ID)
>>          teq   r0, r1
>> +        bne   test_ca7
>>          bleq  cortex_a15_init
>> +        PRINT("- cortex-a15 init done -\r\n")
>> +        b     cpu_init_done
>> +        /* Is this a Cortex A7? */
>> +test_ca7:
>> +        ldr   r1, =(CORTEX_A7_ID)
>> +        teq   r0, r1
>> +        bleq  cortex_a7_init
>> +        PRINT("- cortex-a7 init done -\r\n")
>
> I think now that we have a second processor here it is time to go for a
> more scalable approach. A linker table driven thing, similar to what
> Julien did for the platform (PLATFORM_START et al) or the Linux proc
> table thing seems like the right answer. At the moment it would just
> contain the MIDR mask and match values plus an optional init function
> pointer, in time I suspect it will grow other functionality.
got it. how about add something like __lookup_processor_type and proc-xxx.S
like linux kernel.
>
>> +cpu_init_done:
>>          /* Set up memory attribute type tables */
>>          ldr   r0, =MAIR0VAL
>>          ldr   r1, =MAIR1VAL
>> diff --git a/xen/arch/arm/arm32/proc-ca7.S b/xen/arch/arm/arm32/proc-ca7.S
>> new file mode 100644
>> index 0000000..e0c1bc2
>> --- /dev/null
>> +++ b/xen/arch/arm/arm32/proc-ca7.S
>> @@ -0,0 +1,36 @@
>> +/*
>> + * xen/arch/arm/proc-ca7.S
>> + *
>> + * Cortex A7 specific initializations
>> + *
>> + * Bamvor Jian Zhang <bjzhang@xxxxxxxx>
>> + * Copyright (c) 2013 SUSE
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <asm/asm_defns.h>
>> +#include <asm/processor-ca7.h>
>> +
>> +.globl cortex_a7_init
>> +cortex_a7_init:
>> +        /* Set up the SMP bit in ACTLR */
>> +        mrc   CP32(r0, ACTLR)
>> +        orr   r0, r0, #(ACTLR_CA7_SMP) /* enable SMP bit */
>> +        mcr   CP32(r0, ACTLR)
>> +        mov   pc, lr
>> +
>> +/*
>> + * Local variables:
>> + * mode: ASM
>> + * indent-tabs-mode: nil
>> + * End:
>> + */
>> diff --git a/xen/include/asm-arm/processor-ca7.h 
>> b/xen/include/asm-arm/processor-ca7.h
>> new file mode 100644
>> index 0000000..b773c34
>> --- /dev/null
>> +++ b/xen/include/asm-arm/processor-ca7.h
>> @@ -0,0 +1,25 @@
>> +#ifndef __ASM_ARM_PROCESSOR_CA7_H
>> +#define __ASM_ARM_PROCESSOR_CA7_H
>> +
>> +
>> +#define CORTEX_A7_ID     (0x410FC070)
>> +
>> +/* ACTLR Auxiliary Control Register, Cortex A7 */
>> +#define ACTLR_CA7_DDI                (1<<28)
>> +#define ACTLR_CA7_DDVM               (1<<15)
>> +/* 2 bits */
>> +#define ACTLR_CA7_L1PCTL             (1<<13)
>> +#define ACTLR_CA7_L1RADIS            (1<<12)
>> +#define ACTLR_CA7_L2RADIS            (1<<11)
>> +#define ACTLR_CA7_DODMBS             (1<<10)
>> +#define ACTLR_CA7_SMP                (1<<6)
>
> Is the content of this register really different between A7 and A15?
only SMP bit is same. ACTLR is a implementation defined register.
> At least CA7_SMP is the same as CA15_SMP, which suggests we could share
> the init function (to set the SMP bit) and have both a7 and a15 in the
> same proc-v7.S file.
Ok. i will add proc-v7.S. although i do not know whether a12 is same or not.
we could deal with that later.
>> +
>> +#endif /* __ASM_ARM_PROCESSOR_CA7_H */
>> +/*
>> + * Local variables:
>> + * mode: C
>> + * c-file-style: "BSD"
>> + * c-basic-offset: 4
>> + * indent-tabs-mode: nil
>> + * End:
>> + */


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