Re: [Xen-devel] [V10 PATCH 23/23] PVH xen: introduce vmexit handler for PVH

[Mukesh Rathor <mukesh.rathor@xxxxxxxxxx>]

On Mon, 12 Aug 2013 17:00:36 +0100
George Dunlap <dunlapg@xxxxxxxxx> wrote:

> On Wed, Jul 24, 2013 at 2:59 AM, Mukesh Rathor
> > +/* Returns : 0 == msr read successfully. */
> > +static int vmxit_msr_read(struct cpu_user_regs *regs)
> > +{
> > +    u64 msr_content = 0;
> > +
> > +    switch ( regs->ecx )
> > +    {
> > +    case MSR_IA32_MISC_ENABLE:
> > +        rdmsrl(MSR_IA32_MISC_ENABLE, msr_content);
> > +        msr_content |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |
> > +                       MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
> > +        break;
> > +
> > +    default:
> > +        /* PVH fixme: see hvm_msr_read_intercept(). */
> > +        rdmsrl(regs->ecx, msr_content);
> > +        break;
> 
> So at the moment you basically pass through all MSR reads (adding
> BTS_UNAVAIL and PEBS_UNAVAIL to MISC_ENABLE), but send MSR writes
> through the hvm code?
> 
> That sounds like it's asking for trouble...

Hence the fixme there. I intended to come back to this during AMD
port because of the differences between vmx_ and svm_ msr reads.
In general, we should have less interecepts for PVH, eg, there should
be no MSR_IA32_CR_PAT intercept. If there is nothing specific
for VMX and SVM for PVH, then perhaps a generic solution with may be 
a union or new data struct for PVH....  Anyways, lets divide and conquer
by coming back to this.
...
> > +
> > +        __vmwrite(CR4_READ_SHADOW, new);
> > +
> > +        new &= ~X86_CR4_PAE;         /* PVH always runs with hap
> > enabled. */
> > +        new |= X86_CR4_VMXE | X86_CR4_MCE;
> > +        __vmwrite(GUEST_CR4, new);
> 
> Should you be updating hvm_vcpu.hw_cr[4] to this value?

We dont' use hw_cr[4] for PVH anywhere. I added a comment.

> > +    }
> > +    else
> > +        *regp = __vmread(CR4_READ_SHADOW);
> 
> Same as above re guest_cr[]
> 
We do set it few lines above:

vp->arch.hvm_vcpu.guest_cr[4] = new;


-Mukesh

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