[Xen-devel] [PATCH 3/3] Nested VMX: Fix IA32_VMX_CR4_FIXED1 msr emulation

[Yang Zhang <yang.z.zhang@xxxxxxxxx>]

From: Yang Zhang <yang.z.zhang@xxxxxxxxx>

Currently, it use hardcode value for IA32_VMX_CR4_FIXED1. This is wrong.
We should check guest's cpuid to know which bits are writeable in CR4 by guest
and allow the guest to set the corresponding bit only when guest has the 
feature.

Signed-off-by: Yang Zhang <yang.z.zhang@xxxxxxxxx>
---
 xen/arch/x86/hvm/vmx/vvmx.c |   34 ++++++++++++++++++++++++++++++++--
 1 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 8571002..8e53beb 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1815,6 +1815,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 
*msr_content)
 {
     struct vcpu *v = current;
     u64 data = 0, host_data = 0;
+    unsigned int eax, ebx, ecx, edx;
     int r = 1;
 
     if ( !nestedhvm_enabled(v->domain) )
@@ -1943,8 +1944,37 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 
*msr_content)
         data = X86_CR4_VMXE;
         break;
     case MSR_IA32_VMX_CR4_FIXED1:
-        /* allow 0-settings except SMXE */
-        data = 0x267ff & ~X86_CR4_SMXE;
+        data |= (edx & cpufeat_mask(X86_FEATURE_VME) ?
+                                       (X86_CR4_VME | X86_CR4_PVI) : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_TSC) ? X86_CR4_TSD : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_DE)  ? X86_CR4_DE  : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_PSE) ? X86_CR4_PSE : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_PAE) ? X86_CR4_PAE : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_MCE) ? X86_CR4_MCE : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_PGE) ? X86_CR4_PGE : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_FXSR) ? X86_CR4_OSFXSR : 0) |
+                (edx & cpufeat_mask(X86_FEATURE_XMM) ? X86_CR4_OSXMMEXCPT : 0) 
|
+                (ecx & cpufeat_mask(X86_FEATURE_VMXE) ? X86_CR4_VMXE : 0) |
+                (ecx & cpufeat_mask(X86_FEATURE_SMXE) ? X86_CR4_SMXE : 0) |
+                (ecx & cpufeat_mask(X86_FEATURE_PCID) ? X86_CR4_PCIDE : 0) |
+                (ecx & cpufeat_mask(X86_FEATURE_XSAVE) ? X86_CR4_OSXSAVE : 0);
+
+        hvm_cpuid(0x0, &eax, &ebx, &ecx, &edx);
+        if ( eax >= 0xa )
+        {
+            unsigned int temp_eax;
+
+            hvm_cpuid(0xa, &temp_eax, &ebx, &ecx, &edx);
+            /* Check whether guest has the perf monitor feature. */
+            if ( (temp_eax & 0xff) && (temp_eax & 0xff00) )
+                data |= X86_CR4_PCE;
+        } else if ( eax >= 0x7 )
+        {
+            hvm_cpuid(0x7, &eax, &ebx, &ecx, &edx);
+            data |= (ebx & cpufeat_mask(X86_FEATURE_SMEP) ? X86_CR4_SMEP : 0) |
+                    (ebx & cpufeat_mask(X86_FEATURE_FSGSBASE) ?
+                                              X86_CR4_FSGSBASE : 0);
+        }
         break;
     case MSR_IA32_VMX_MISC:
         /* Do not support CR3-target feature now */
-- 
1.7.1


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