Re: [Xen-devel] Multi-bridged PCIe devices (Was: Re: iommuu/vt-d issues with LSI MegaSAS (PERC5i))

[Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>]

On Tue, Jan 07, 2014 at 02:47:23PM +0000, Jan Beulich wrote:
> >>> On 07.01.14 at 15:38, Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx> 
> >>> wrote:
> > That requires knowing the MMIO BARs the 'fake' device has, and
> > .. well, whatever else the Intel VT-d code requires.
> 
> Why would you need to know BAR values? Weren't we talking of
> an invisible bridge (in which case one would expect that there's
> no MSI-X interrupts to be used, which is the only reason I can
> see us needing to know/read the BARs)?

I mispoke. I was thinking about the 'memory behind the bridge'
is what I need to add in somehwere.

I really need to look at the VT-d spec and implementation to see
what data I need to provide to it.

> 
> Jan
> 

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