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Re: [Xen-devel] [RFC v3 2/6] xen/arm: Add save/restore support for ARM GIC V2
- To: Ian Campbell <Ian.Campbell@xxxxxxxxxx>, Wei Huang <w1.huang@xxxxxxxxxxx>
- From: Julien Grall <julien.grall@xxxxxxxxxx>
- Date: Sun, 11 May 2014 17:15:26 +0100
- Cc: keir@xxxxxxx, stefano.stabellini@xxxxxxxxxxxxx, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, tim@xxxxxxx, jaeyong.yoo@xxxxxxxxxxx, xen-devel@xxxxxxxxxxxxx, jbeulich@xxxxxxxx, ian.jackson@xxxxxxxxxxxxx, yjhyun.yoo@xxxxxxxxxxx
- Delivery-date: Sun, 11 May 2014 18:33:41 +0000
- List-id: Xen developer discussion <xen-devel.lists.xen.org>
Hi,
On 09/05/14 15:24, Ian Campbell wrote:
On Fri, 2014-05-09 at 09:12 -0500, Wei Huang wrote:
On 05/08/2014 05:47 PM, Andrew Cooper wrote:
+DECLARE_HVM_SAVE_TYPE(GICH_V2, 3, struct hvm_arm_gich_v2);
+
/*
* Largest type-code in use
*/
-#define HVM_SAVE_CODE_MAX 1
+#define HVM_SAVE_CODE_MAX 3
#endif
On x86, we require that HVM save records only contain architectural
state. Not knowing arm myself, it is not clear from your comments
whether this is the case or not. Can you confirm whether it is or not?
Most states are guest architecture states which include core registers,
arch timer, memory. GIC states are arguable, given that Xen uses data
structures (e.g. struct vgic_irq_rank) to represent GIC states internally.
(note: I've not looked at this series for ages, I plan to look at this
new version next week)
The contents of vgic_irq_rank is still a set of architectural register,
I think (the rank thing is just to account for the fact that some
registers use 1 bit to describe 32-registers, some use 2 bits to
describe 16, etc).
Correct, the vgic_irq_rank should be saved entirely. It represents the
guest view of the GIC state (such as the priorities, the routing... of
an IRQ).
Regards,
--
Julien Grall
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