[Xen-devel] [PATCH v2 07/10] x86/boot: Correct CR4 setup on APs

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

It is not safe to load mmu_cr4_features into cr4 early on AP start.  Features
such as MCE require an int 0x18 handler to be set up.

Instead, load the minimum Xen CR4 features early but defer loading the full
'mmu_cr4_features' set until after the IDT has been set up.

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CC: Keir Fraser <keir@xxxxxxx>
CC: Jan Beulich <JBeulich@xxxxxxxx>
CC: Tim Deegan <tim@xxxxxxx>
---
 xen/arch/x86/boot/x86_64.S      |    4 ++--
 xen/arch/x86/setup.c            |    3 +--
 xen/arch/x86/smpboot.c          |    4 +++-
 xen/include/asm-x86/processor.h |    2 ++
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 67dfef9..417623f 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -9,8 +9,8 @@
         mov     %ecx,%gs
         mov     %ecx,%ss
 
-        /* Enable full CR4 features. */
-        mov     mmu_cr4_features(%rip),%rcx
+        /* Enable minimal CR4 features. */
+        mov     $XEN_MINIMAL_CR4,%rcx
         mov     %rcx,%cr4
 
         mov     stack_start(%rip),%rsp
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 5fc71d5..b2a808a 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -100,8 +100,7 @@ char __attribute__ ((__section__(".bss.stack_aligned"))) 
cpu0_stack[STACK_SIZE];
 
 struct cpuinfo_x86 __read_mostly boot_cpu_data = { 0, 0, 0, 0, -1 };
 
-unsigned long __read_mostly mmu_cr4_features =
-    X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE;
+unsigned long __read_mostly mmu_cr4_features = XEN_MINIMAL_CR4;
 
 bool_t __initdata acpi_disabled;
 bool_t __initdata acpi_force;
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index c2c8752..84f2d25 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -318,7 +318,6 @@ void start_secondary(void *unused)
     this_cpu(curr_vcpu) = idle_vcpu[cpu];
     if ( cpu_has_efer )
         rdmsrl(MSR_EFER, this_cpu(efer));
-    asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
 
     /*
      * Just as during early bootstrap, it is convenient here to disable
@@ -342,6 +341,9 @@ void start_secondary(void *unused)
 
     /* Full exception support from here on in. */
 
+    /* Safe to enable feature such as CR4.MCE with the IDT set up now. */
+    write_cr4(mmu_cr4_features);
+
     percpu_traps_init();
 
     init_percpu_time();
diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index c9051be..805ec34 100644
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -141,6 +141,8 @@
 #define PFEC_page_paged     (1U<<5)
 #define PFEC_page_shared    (1U<<6)
 
+#define XEN_MINIMAL_CR4 (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE)
+
 #define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF|    \
                           X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF|    \
                           X86_EFLAGS_TF)
-- 
1.7.10.4


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