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Re: [Xen-devel] [PATCH 1/2] x86/mem_event: Deliver gla fault EPT violation information
- To: Tamas Lengyel <tamas.lengyel@xxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Thu, 7 Aug 2014 18:34:07 +0100
- Cc: kevin.tian@xxxxxxxxx, Ian Campbell <ian.campbell@xxxxxxxxxx>, Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>, Ian Jackson <ian.jackson@xxxxxxxxxxxxx>, eddie.dong@xxxxxxxxx, Aravind.Gopalakrishnan@xxxxxxx, Jun Nakajima <jun.nakajima@xxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, boris.ostrovsky@xxxxxxxxxx, suravee.suthikulpanit@xxxxxxx
- Delivery-date: Thu, 07 Aug 2014 17:37:02 +0000
- List-id: Xen developer discussion <xen-devel.lists.xen.org>
On 07/08/14 18:14, Tamas Lengyel wrote:
According to the Intel manual the gla_fault bit is
only set if bit 7 (gla_valid) is 1 and it is reserved if bit 7
is 0 (cleared to 0). So the combination of gla_valid = 0 and
gla_fault = 0 is safe to use as a fallback. Furthermore, there
is no mem_access support for AMD NPT so at this point this is
just a placeholder in the svm code.
That is entirely my point. You are putting Intel-isms in a common
interface which AMD currently cant use, and might cause issues for
someone trying to reintroduce feature parity.
I think at a minimum, I think you need a gla_fault_info_valid bit
unless you can guarentee that AMD NPT will never gain the ability to
report a valid gla. (I don't know whether it can or not. Looking at
the code, it would appear that it can't currently, but I certainly
not bet against it ever gaining this ability.)
~Andrew
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