[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH v2] x86/intel: Protect set_cpuidmask() against #GP faults
> From: Tian, Kevin > Sent: Friday, August 08, 2014 1:57 PM > > v2: Correct msr_val manipulation for msr_xsave > > > > Can anyone shed light as to which CPU model 0x1f is? It is specified in the > > flexmigrate document, and was present in the old code, but I can't find any > > further information online. > > 0x1f is a Nehalem model (See SDM vol3. 35.5). I'll check whether a concrete > name is available. > and from SDM vol3. 35.1, it's Core i7/i5 processors with Nehalem micro-arch. Thanks Kevin _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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