Re: [Xen-devel] [V0 PATCH 1/6] AMD-PVH: construct vmcb changes

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On 16/08/14 03:53, Mukesh Rathor wrote:
> PVH guest starts in Long 64bit paging mode. This patch modifies
> construct_vmcb for that.
> 
> Signed-off-by: Mukesh Rathor <mukesh.rathor@xxxxxxxxxx>
> ---
>  xen/arch/x86/hvm/svm/vmcb.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
> index 21292bb..5df5f36 100644
> --- a/xen/arch/x86/hvm/svm/vmcb.c
> +++ b/xen/arch/x86/hvm/svm/vmcb.c
> @@ -138,6 +138,8 @@ static int construct_vmcb(struct vcpu *v)
>  
>      /* Guest EFER. */
>      v->arch.hvm_vcpu.guest_efer = 0;
> +    if ( is_pvh_vcpu(v) )
> +        v->arch.hvm_vcpu.guest_efer |= EFER_LMA;   /* PVH 32bitfixme */
>      hvm_update_guest_efer(v);
>  
>      /* Guest segment limits. */
> @@ -162,7 +164,12 @@ static int construct_vmcb(struct vcpu *v)
>      vmcb->ds.attr.bytes = 0xc93;
>      vmcb->fs.attr.bytes = 0xc93;
>      vmcb->gs.attr.bytes = 0xc93;
> -    vmcb->cs.attr.bytes = 0xc9b; /* exec/read, accessed */
> +
> +    if ( is_pvh_vcpu(v) )
> +        /* CS.L == 1, exec, read/write, accessed. PVH 32bitfixme. */
> +        vmcb->cs.attr.bytes = 0xa9b;
> +    else
> +        vmcb->cs.attr.bytes = 0xc9b; /* exec/read, accessed */
>  
>      /* Guest IDT. */
>      vmcb->idtr.base = 0;
> @@ -184,12 +191,17 @@ static int construct_vmcb(struct vcpu *v)
>      vmcb->tr.limit = 0xff;
>  
>      v->arch.hvm_vcpu.guest_cr[0] = X86_CR0_PE | X86_CR0_ET;
> +    /* PVH domains start in paging mode */
> +    if ( is_pvh_vcpu(v) )
> +        v->arch.hvm_vcpu.guest_cr[0] |= X86_CR0_PG;
>      hvm_update_guest_cr(v, 0);
>  
> -    v->arch.hvm_vcpu.guest_cr[4] = 0;
> +    v->arch.hvm_vcpu.guest_cr[4] = is_pvh_vcpu(v) ? X86_CR4_PAE : 0;
>      hvm_update_guest_cr(v, 4);
>  
> -    paging_update_paging_modes(v);
> +    /* For pvh, paging mode is updated by arch_set_info_guest(). */
> +    if ( is_hvm_vcpu(v) )
> +        paging_update_paging_modes(v);
>  
>      vmcb->_exception_intercepts =
>          HVM_TRAP_MASK


I know this is already done on Intel in order to boot PVH guests, but
now that we know what we need to modify in both Intel and AMD HVM code,
do you think it would we suitable to add another parameter to
vcpu_initialise in order to tell it to setup the vcpu to boot into long
(or protected if we support 32bit PVH guests) mode (and prevent adding
more is_pvh_vcpu)?

Roger.

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