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Re: [Xen-devel] x2APIC MSR range (XSA-108 follow-up)

On Tue, Oct 14, 2014 at 06:23:52AM +0000, Zhang, Yang Z wrote:
> Wu, Feng wrote on 2014-10-14:
> > 
> > The SDM says:
> > 
> > " Addresses in the range 800H¨CBFFH that are not listed in Table 10-6
> > (including 80EH and 831H) are reserved.
> > Executions of RDMSR and WRMSR that attempt to access such addresses
> > cause general-protection exceptions. "
> > 
> > Table 10-6. Local APIC Register Address Map Supported by x2APIC
> > 
> > Why should we virtualize those reserved MSRs for guests?
> IIUC the question should be why those undocumented MSRs exist on
> real hardware and what do they do? Will guest access to them via
> check CPU model? If yes, how can we virtualize them correctly?

I suspect that Intel knows what they are and what they do. I imagine
that both are CPU model specific.

> I don't have the answer right now but I will forward the question to
> hardware guy for more help.

Since these MSRs are not part of the SDM or any public platform
documentation as far as I can tell, I imagine that they are for
BIOS-level functionality that does not have meaning in a virtual
environment today and presents no OS compatibility problem if we
choose to #GP all access to them.

Short of some reply from Intel saying "No! That will break some OS" I
think that we should make the x2APIC MSR code handle 0x800...0xbff and
#GP any access that is above the emulated area.


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