[Xen-devel] [PATCH] xen: arm64: more useful logging on bad trap.

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

Dump the register state before panicing so we have some clue where the
issue occurred. Also decode the ESR register a bit to save having to
grab a pen and paper.

ESR_EL2 is a 32-bit register, so use SYSREG_READ32 not ..._READ64, as
we already do correctly in the main trap handler.

While here notice that do_trap_serror is never called and remove it.

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Cc: jintack@xxxxxxxxxxxxxxx
---
Jintack, since you have a system which is exhibiting SError issues I
wonder if I could prevail on you to give this patch a try on your
system and report on the output. I've only compile tested this myself.
---
 xen/arch/arm/arm64/traps.c |   13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c
index 1693b5d..89b8eb3 100644
--- a/xen/arch/arm/arm64/traps.c
+++ b/xen/arch/arm/arm64/traps.c
@@ -24,11 +24,6 @@
 
 #include <public/xen.h>
 
-asmlinkage void do_trap_serror(struct cpu_user_regs *regs)
-{
-    panic("Unhandled serror trap");
-}
-
 static const char *handler[]= {
         "Synchronous Abort",
         "IRQ",
@@ -38,11 +33,13 @@ static const char *handler[]= {
 
 asmlinkage void do_bad_mode(struct cpu_user_regs *regs, int reason)
 {
-    uint64_t esr = READ_SYSREG64(ESR_EL2);
-    printk("Bad mode in %s handler detected, code 0x%08"PRIx64"\n",
-           handler[reason], esr);
+    union hsr hsr = { .bits = READ_SYSREG32(ESR_EL2) };
+    printk("Bad mode in %s handler detected, code 0x%08"PRIx32","
+           " EC=%"PRIx32", IL=%"PRIx32" ISS=%"PRIx32"\n",
+           handler[reason], hsr.bits, hsr.ec, hsr.len, hsr.iss);
 
     local_irq_disable();
+    show_execution_state(regs);
     panic("bad mode");
 }
 
-- 
1.7.10.4


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