[Xen-devel] [PATCH 2/3] mwait-idle: update support for Silvermont Core in Baytrail SOC

["Jan Beulich" <JBeulich@xxxxxxxx>]

On some Silvermont-Core/Baytrail-SOC systems,
C1E latency is higher than original specifications.
Although C1E is still enumerated in CPUID.MWAIT.EDX,
we delete the state from intel_idle to avoid latency impact.

Under some conditions, the latency of the C6N-BYT and C6S-BYT states
may exceed the specified values of 40 and 140 usec, respectively.
Increase those values to 300 and 500 usec; to assure
that the hardware does not violate constraints that may be set
by the Linux PM_QOS sub-system.

Also increase the C7-BYT target residency to 4.0 ms from 1.5 ms.

Signed-off-by: Len Brown <len.brown@xxxxxxxxx>
[Linux commit d7ef76717322c8e2df7d4360b33faa9466cb1a0d]
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -196,28 +196,22 @@ static const struct cpuidle_state byt_cs
                .target_residency = 1,
        },
        {
-               .name = "C1E-BYT",
-               .flags = MWAIT2flg(0x01),
-               .exit_latency = 15,
-               .target_residency = 30,
-       },
-       {
                .name = "C6N-BYT",
                .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
-               .exit_latency = 40,
+               .exit_latency = 300,
                .target_residency = 275,
        },
        {
                .name = "C6S-BYT",
                .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
-               .exit_latency = 140,
+               .exit_latency = 500,
                .target_residency = 560,
        },
        {
                .name = "C7-BYT",
                .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
                .exit_latency = 1200,
-               .target_residency = 1500,
+               .target_residency = 4000,
        },
        {
                .name = "C7S-BYT",

Attachment: mwait-idle-Baytrail-no-C1E.patch
Description: Text document

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