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Re: [Xen-devel] [PATCH v2.5 31/30] Fix PV guest XSAVE handling with levelling

On 17/02/16 09:02, Jan Beulich wrote:
>>>> On 08.02.16 at 18:26, <andrew.cooper3@xxxxxxxxxx> wrote:
> This fiddles with behavior on AMD only, yet it's not obvious why this
> couldn't be done in vendor independent code (it should, afaict, be
> benign for Intel).

AMD and Intel levelling are fundamentally different.

The former are override MSRs with some quirks when it comes to the magic
bits, while the latter are strict masks which take effect before the
magic bits are folded in.


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