[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCHv2 2/3] x86/fpu: Add a per-domain field to set the width of FIP/FDP
>>> On 23.02.16 at 17:27, <david.vrabel@xxxxxxxxxx> wrote: > On 23/02/16 15:24, Jan Beulich wrote: >>>>> On 23.02.16 at 12:05, <david.vrabel@xxxxxxxxxx> wrote: >>> @@ -292,17 +296,17 @@ void xsave(struct vcpu *v, uint64_t mask) >>> asm volatile ( "fnstenv %0" : "=m" (fpu_env) ); >>> ptr->fpu_sse.fip.sel = fpu_env.fcs; >>> ptr->fpu_sse.fdp.sel = fpu_env.fds; >>> - word_size = 4; >>> + fip_width = 4; >>> } >>> + else >>> + fip_width = 8; >>> } >>> else >>> { >>> XSAVE(""); >>> - word_size = 4; >>> } >>> #undef XSAVE >>> - if ( word_size >= 0 ) >>> - ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] = word_size; >>> + ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] = fip_width; >>> } >> >> There's actually a pre-existing bug here that I think should get >> fixed at once: The 64-bit save path avoided to update >> ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] when FPU state >> didn't get saved (by setting word_size to -1), which continues to be >> the case due to patch 1's changes. The 32-bit code path violated >> this even before your change. I.e. the last else visible above >> should get extended to return when !(mask & XSTATE_FP). > > XSTATE_FP is always set in the mask. (see fpu_xsave()). fpu_xsave() sets the flag in XCR0, but not all values returned from vcpu_xsave_mask() have that flag set (and hence the "mask" parameter doesn't either). Jan _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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