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Re: [Xen-devel] [PATCH RFC 0/8] x86/hvm, libxl: HVM SMT topology support



On Fri, 2016-02-26 at 10:27 -0500, Konrad Rzeszutek Wilk wrote:
> On Fri, Feb 26, 2016 at 04:03:46PM +0100, Dario Faggioli wrote:
>
> > > As part of my further cpuid work, I will need to fix this.  I was
> > > planning to fix it by requiring full cpu topology information to
> > > be
> > > passed as part of the domaincreate or max_vcpus hypercall  (not
> > > chosen
> > > which yet).  
> 
> You may not want to make a full CPU topology to be exposed to the
> guest.
> 
Right, but if I understood correctly (and, actually, to confirm that is
what I'm asking), what's Andrew is saying does not mean "always expose
the host topology". It means that a guest must have a (virtual)
topology, and that topology can be Xen's default one, toolstack's
default one, toolstack's default one when vcpu pinning is on, one that
the administrator like, etc.

> Elena (CCed) found some oddities and it actually looked like the
> guest
> performed _worst_ when it had this exposed and was floating (not-
> pinned)
> on machines with SMT enabled.
> 
Well, sure, that's something I would entirely expect. And in fact, more
than better or worst, I remember the numbers you (well, she) posted to
prove that exposing topology and letting the vcpu free to float leads
to inconsistency and lack of predictability, which again is what I'd
have predicted. :-)

> > At that point, one can just build on top of that, in order to
> > achieve
> > something like what is implemented in this series, or any other
> > variant
> > of it, which would indeed be *awesome* (did I said that already? :-
> > D).
> Maybe you should lay off the coffee for a bit ..
> 
I also think that... but, you know, I'm in Italy, and here it's a crime
not to have at least 4 coffees (== espresso, of course!) during the
day! ;-)

Regards,
Dario
-- 
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)

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