Re: [Xen-devel] [PATCHv3 1/3] x86/fpu: improve check for XSAVE* not writing FIP/FDP fields

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

> From: Jan Beulich
> Sent: Thursday, February 25, 2016 8:28 PM
> 
> >>
> >> Pending confirmation on FIP register width by at least Intel,
> >> Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
> >
> > For Intel CPUs, FIP is 48-bits internally and newer CPUs have FPCSDS and
> > thus we will always use the 64-bit save.
> 
> Has Intel told you (but not us), or is this just based on experiments
> you did, or re-stating what I've found from experimenting?
> 

Still wait for an internal clarification... but could I think this
question is more for older CPUs which don't claim FPCSDS
since otherwise no such trick is required with 64bit save/restore?

Thanks
Kevin
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