|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCHv3 1/3] x86/fpu: improve check for XSAVE* not writing FIP/FDP fields
>>> On 01.03.16 at 07:27, <kevin.tian@xxxxxxxxx> wrote: >> From: Jan Beulich >> Sent: Thursday, February 25, 2016 8:28 PM >> >> >> >> >> Pending confirmation on FIP register width by at least Intel, >> >> Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx> >> > >> > For Intel CPUs, FIP is 48-bits internally and newer CPUs have FPCSDS and >> > thus we will always use the 64-bit save. >> >> Has Intel told you (but not us), or is this just based on experiments >> you did, or re-stating what I've found from experimenting? >> > > Still wait for an internal clarification... but could I think this > question is more for older CPUs which don't claim FPCSDS > since otherwise no such trick is required with 64bit save/restore? Yes, the question regards just CPUs storing non-zero selector values. Yet with that functionality being dropped having an impact on migration of Windows guests, I'm not actually sure you can retain the decision to no longer store these selectors without the OS (or hypervisor in our case) explicitly stating its consent (via some control register bit). Jan _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
|
 |
Lists.xenproject.org is hosted with RackSpace, monitoring our |