[Xen-devel] [PATCH] X86/VPMU: mask off uncore overflow bit on xeon phi knights landing

[Luwei Kang <luwei.kang@xxxxxxxxx>]

IA32_PERF_GLOBAL_STATUS.OvfUncore (MSR 38EH, bit[61]) is always 0 and
writing 1 to IA32_PERF_GLOBAL_OVF_CTRL.ClrOvfUncore (MSR 390H, bit[61])
signals #GP.
Reference "Intel Xeon Phi Procssor x200 Product Family", document
number 334646-008.

Signed-off-by: Luwei Kang <luwei.kang@xxxxxxxxx>
---
 xen/arch/x86/cpu/vpmu_intel.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index e8049ed..0be78ff 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -1058,11 +1058,17 @@ int __init core2_vpmu_init(void)
                              (((1ULL << fixed_pmc_cnt) - 1) << 32) |
                              ((1ULL << arch_pmc_cnt) - 1));
     if ( version > 2 )
+    {
         /*
          * Even though we don't support Uncore counters guests should be
          * able to clear all available overflows.
          */
         global_ovf_ctrl_mask &= ~(1ULL << 61);
+        /* Knight Landing doesn't support overflow bit on uncore counters */
+        if ( current_cpu_data.x86_model == 0x57 )
+            global_ovf_ctrl_mask |= (1ULL << 61);
+
+    }
 
     regs_sz = (sizeof(struct xen_pmu_intel_ctxt) - regs_off) +
               sizeof(uint64_t) * fixed_pmc_cnt +
-- 
1.8.3.1


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