Re: [Xen-devel] [PATCH v3] x86/vpmu_intel: Fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 04.05.17 at 23:30, <mohit.gambhir@xxxxxxxxxx> wrote:
> Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General
> Protection Fault and thus results in a hypervisor crash. This behavior has
> been observed on two generations of Intel processors namely, Haswell and
> Broadwell. Other Intel processor generations were not tested. However, it
> does seem to be a possible erratum that hasn't yet been confirmed by Intel.
> 
> To fix the problem this patch masks PC bit and returns an error in
> case any guest tries to write to it on any Intel processor. In addition
> to the fact that setting this bit crashes the hypervisor on Haswell and
> Broadwell, the PC flag bit toggles a hardware pin on the physical CPU
> every time the programmed event occurs and the hardware behavior in
> response to the toggle is undefined in the SDM, which makes this bit
> unsafe to be used by guests and hence should be masked on all machines.
> 
> Signed-off-by: Mohit Gambhir <mohit.gambhir@xxxxxxxxxx>

Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>

Iirc the intention was to have this in 4.9, in which case you should
have Cc-ed Juline (now added).

Jan


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